diff options
Diffstat (limited to 'meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/0192-drm-amd-display-add-dcfclk-reporting-to-pplib.patch')
-rw-r--r-- | meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/0192-drm-amd-display-add-dcfclk-reporting-to-pplib.patch | 111 |
1 files changed, 111 insertions, 0 deletions
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/0192-drm-amd-display-add-dcfclk-reporting-to-pplib.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/0192-drm-amd-display-add-dcfclk-reporting-to-pplib.patch new file mode 100644 index 00000000..932a5d6d --- /dev/null +++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/0192-drm-amd-display-add-dcfclk-reporting-to-pplib.patch @@ -0,0 +1,111 @@ +From 62370bef822e99dcd31eb21987d144db503f1d60 Mon Sep 17 00:00:00 2001 +From: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> +Date: Wed, 25 Jan 2017 13:58:46 -0500 +Subject: [PATCH 0192/4131] drm/amd/display: add dcfclk reporting to pplib + +Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> +Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> +Acked-by: Harry Wentland <Harry.Wentland@amd.com> +Signed-off-by: Alex Deucher <alexander.deucher@amd.com> +--- + drivers/gpu/drm/amd/display/dc/core/dc.c | 48 +++++++++---------------- + drivers/gpu/drm/amd/display/dc/inc/core_types.h | 1 + + 2 files changed, 18 insertions(+), 31 deletions(-) + +diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c +index e05e419..9d2f78f 100644 +--- a/drivers/gpu/drm/amd/display/dc/core/dc.c ++++ b/drivers/gpu/drm/amd/display/dc/core/dc.c +@@ -1065,7 +1065,7 @@ bool dc_pre_update_surfaces_to_stream( + { + int i, j; + struct core_dc *core_dc = DC_TO_CORE(dc); +- uint32_t prev_disp_clk = core_dc->current_context->bw_results.dispclk_khz; ++ int prev_disp_clk = core_dc->current_context->bw_results.dispclk_khz; + int new_disp_clk; + struct dc_stream_status *stream_status = NULL; + struct validate_context *context; +@@ -1146,36 +1146,23 @@ bool dc_pre_update_surfaces_to_stream( + } + } + +- if (core_dc->res_pool->funcs->validate_bandwidth(core_dc, context) != DC_OK) { +- BREAK_TO_DEBUGGER(); +- ret = false; +- goto unexpected_fail; +- } +- new_disp_clk = context->bw_results.dispclk_khz; +- +- if (core_dc->res_pool->funcs->apply_clk_constraints) { +- temp_context = core_dc->res_pool->funcs->apply_clk_constraints( +- core_dc, +- context); +- if (!temp_context) { +- dm_error("%s:failed apply clk constraints\n", __func__); ++ if (core_dc->res_pool->funcs->validate_bandwidth) ++ if (core_dc->res_pool->funcs->validate_bandwidth(core_dc, context) != DC_OK) { ++ BREAK_TO_DEBUGGER(); + ret = false; + goto unexpected_fail; + } +- resource_validate_ctx_destruct(context); +- ASSERT(core_dc->scratch_val_ctx == temp_context); +- core_dc->scratch_val_ctx = context; +- context = temp_context; +- } ++ new_disp_clk = context->bw_results.dispclk_khz; + +- if (prev_disp_clk < new_disp_clk) { ++ if (!IS_FPGA_MAXIMUS_DC(core_dc->ctx->dce_environment) ++ && prev_disp_clk < new_disp_clk) { + pplib_apply_display_requirements(core_dc, context, + &context->pp_display_cfg); + context->res_ctx.pool->display_clock->funcs->set_clock( + context->res_ctx.pool->display_clock, +- context->bw_results.dispclk_khz * 115 / 100); +- core_dc->current_context->bw_results.dispclk_khz = +- context->bw_results.dispclk_khz; ++ new_disp_clk * 115 / 100); ++ core_dc->current_context->bw_results.dispclk_khz = new_disp_clk; ++ core_dc->current_context->dispclk_khz = new_disp_clk; + } + + for (i = 0; i < new_surface_count; i++) +@@ -1209,15 +1196,14 @@ bool dc_post_update_surfaces_to_stream(struct dc *dc) + if (core_dc->current_context->res_ctx.pipe_ctx[i].stream == NULL) { + core_dc->current_context->res_ctx.pipe_ctx[i].pipe_idx = i; + core_dc->hwss.power_down_front_end( +- core_dc, &core_dc->current_context->res_ctx.pipe_ctx[i]); ++ core_dc, &core_dc->current_context->res_ctx.pipe_ctx[i]); ++ } ++ if (core_dc->res_pool->funcs->validate_bandwidth) ++ if (core_dc->res_pool->funcs->validate_bandwidth( ++ core_dc, core_dc->current_context) != DC_OK) { ++ BREAK_TO_DEBUGGER(); ++ return false; + } +- +- +- if (core_dc->res_pool->funcs->validate_bandwidth(core_dc, core_dc->current_context) +- != DC_OK) { +- BREAK_TO_DEBUGGER(); +- return false; +- } + + core_dc->hwss.set_bandwidth(core_dc); + +diff --git a/drivers/gpu/drm/amd/display/dc/inc/core_types.h b/drivers/gpu/drm/amd/display/dc/inc/core_types.h +index 1a81e83..124df67 100644 +--- a/drivers/gpu/drm/amd/display/dc/inc/core_types.h ++++ b/drivers/gpu/drm/amd/display/dc/inc/core_types.h +@@ -316,6 +316,7 @@ struct validate_context { + struct bw_calcs_output bw_results; + /* Note: these are big structures, do *not* put on stack! */ + struct dm_pp_display_configuration pp_display_cfg; ++ int dispclk_khz; + }; + + #endif /* _CORE_TYPES_H_ */ +-- +2.7.4 + |