diff options
Diffstat (limited to 'meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/0015-drm-amdgpu-gfx8-drop-cz-mqd.patch')
-rw-r--r-- | meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/0015-drm-amdgpu-gfx8-drop-cz-mqd.patch | 287 |
1 files changed, 287 insertions, 0 deletions
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/0015-drm-amdgpu-gfx8-drop-cz-mqd.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/0015-drm-amdgpu-gfx8-drop-cz-mqd.patch new file mode 100644 index 00000000..04950108 --- /dev/null +++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/0015-drm-amdgpu-gfx8-drop-cz-mqd.patch @@ -0,0 +1,287 @@ +From 6a75ee5116245ff5b082294f7c42c55b031f2d0f Mon Sep 17 00:00:00 2001 +From: Alex Deucher <alexander.deucher@amd.com> +Date: Thu, 24 Aug 2017 16:47:15 -0400 +Subject: [PATCH 0015/4131] drm/amdgpu/gfx8: drop cz mqd + +It was unused and according to hw team, it's the same for +all asics in a gfx family so remove it. + +Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> +Signed-off-by: Alex Deucher <alexander.deucher@amd.com> +--- + drivers/gpu/drm/amd/include/vi_structs.h | 259 ------------------------------- + 1 file changed, 259 deletions(-) + +diff --git a/drivers/gpu/drm/amd/include/vi_structs.h b/drivers/gpu/drm/amd/include/vi_structs.h +index 3e606a7..2023482 100644 +--- a/drivers/gpu/drm/amd/include/vi_structs.h ++++ b/drivers/gpu/drm/amd/include/vi_structs.h +@@ -423,265 +423,6 @@ struct vi_mqd_allocation { + uint32_t dynamic_rb_mask; + }; + +-struct cz_mqd { +- uint32_t header; +- uint32_t compute_dispatch_initiator; +- uint32_t compute_dim_x; +- uint32_t compute_dim_y; +- uint32_t compute_dim_z; +- uint32_t compute_start_x; +- uint32_t compute_start_y; +- uint32_t compute_start_z; +- uint32_t compute_num_thread_x; +- uint32_t compute_num_thread_y; +- uint32_t compute_num_thread_z; +- uint32_t compute_pipelinestat_enable; +- uint32_t compute_perfcount_enable; +- uint32_t compute_pgm_lo; +- uint32_t compute_pgm_hi; +- uint32_t compute_tba_lo; +- uint32_t compute_tba_hi; +- uint32_t compute_tma_lo; +- uint32_t compute_tma_hi; +- uint32_t compute_pgm_rsrc1; +- uint32_t compute_pgm_rsrc2; +- uint32_t compute_vmid; +- uint32_t compute_resource_limits; +- uint32_t compute_static_thread_mgmt_se0; +- uint32_t compute_static_thread_mgmt_se1; +- uint32_t compute_tmpring_size; +- uint32_t compute_static_thread_mgmt_se2; +- uint32_t compute_static_thread_mgmt_se3; +- uint32_t compute_restart_x; +- uint32_t compute_restart_y; +- uint32_t compute_restart_z; +- uint32_t compute_thread_trace_enable; +- uint32_t compute_misc_reserved; +- uint32_t compute_dispatch_id; +- uint32_t compute_threadgroup_id; +- uint32_t compute_relaunch; +- uint32_t compute_wave_restore_addr_lo; +- uint32_t compute_wave_restore_addr_hi; +- uint32_t compute_wave_restore_control; +- uint32_t reserved_39; +- uint32_t reserved_40; +- uint32_t reserved_41; +- uint32_t reserved_42; +- uint32_t reserved_43; +- uint32_t reserved_44; +- uint32_t reserved_45; +- uint32_t reserved_46; +- uint32_t reserved_47; +- uint32_t reserved_48; +- uint32_t reserved_49; +- uint32_t reserved_50; +- uint32_t reserved_51; +- uint32_t reserved_52; +- uint32_t reserved_53; +- uint32_t reserved_54; +- uint32_t reserved_55; +- uint32_t reserved_56; +- uint32_t reserved_57; +- uint32_t reserved_58; +- uint32_t reserved_59; +- uint32_t reserved_60; +- uint32_t reserved_61; +- uint32_t reserved_62; +- uint32_t reserved_63; +- uint32_t reserved_64; +- uint32_t compute_user_data_0; +- uint32_t compute_user_data_1; +- uint32_t compute_user_data_2; +- uint32_t compute_user_data_3; +- uint32_t compute_user_data_4; +- uint32_t compute_user_data_5; +- uint32_t compute_user_data_6; +- uint32_t compute_user_data_7; +- uint32_t compute_user_data_8; +- uint32_t compute_user_data_9; +- uint32_t compute_user_data_10; +- uint32_t compute_user_data_11; +- uint32_t compute_user_data_12; +- uint32_t compute_user_data_13; +- uint32_t compute_user_data_14; +- uint32_t compute_user_data_15; +- uint32_t cp_compute_csinvoc_count_lo; +- uint32_t cp_compute_csinvoc_count_hi; +- uint32_t reserved_83; +- uint32_t reserved_84; +- uint32_t reserved_85; +- uint32_t cp_mqd_query_time_lo; +- uint32_t cp_mqd_query_time_hi; +- uint32_t cp_mqd_connect_start_time_lo; +- uint32_t cp_mqd_connect_start_time_hi; +- uint32_t cp_mqd_connect_end_time_lo; +- uint32_t cp_mqd_connect_end_time_hi; +- uint32_t cp_mqd_connect_end_wf_count; +- uint32_t cp_mqd_connect_end_pq_rptr; +- uint32_t cp_mqd_connect_end_pq_wptr; +- uint32_t cp_mqd_connect_end_ib_rptr; +- uint32_t reserved_96; +- uint32_t reserved_97; +- uint32_t cp_mqd_save_start_time_lo; +- uint32_t cp_mqd_save_start_time_hi; +- uint32_t cp_mqd_save_end_time_lo; +- uint32_t cp_mqd_save_end_time_hi; +- uint32_t cp_mqd_restore_start_time_lo; +- uint32_t cp_mqd_restore_start_time_hi; +- uint32_t cp_mqd_restore_end_time_lo; +- uint32_t cp_mqd_restore_end_time_hi; +- uint32_t reserved_106; +- uint32_t reserved_107; +- uint32_t gds_cs_ctxsw_cnt0; +- uint32_t gds_cs_ctxsw_cnt1; +- uint32_t gds_cs_ctxsw_cnt2; +- uint32_t gds_cs_ctxsw_cnt3; +- uint32_t reserved_112; +- uint32_t reserved_113; +- uint32_t cp_pq_exe_status_lo; +- uint32_t cp_pq_exe_status_hi; +- uint32_t cp_packet_id_lo; +- uint32_t cp_packet_id_hi; +- uint32_t cp_packet_exe_status_lo; +- uint32_t cp_packet_exe_status_hi; +- uint32_t gds_save_base_addr_lo; +- uint32_t gds_save_base_addr_hi; +- uint32_t gds_save_mask_lo; +- uint32_t gds_save_mask_hi; +- uint32_t ctx_save_base_addr_lo; +- uint32_t ctx_save_base_addr_hi; +- uint32_t reserved_126; +- uint32_t reserved_127; +- uint32_t cp_mqd_base_addr_lo; +- uint32_t cp_mqd_base_addr_hi; +- uint32_t cp_hqd_active; +- uint32_t cp_hqd_vmid; +- uint32_t cp_hqd_persistent_state; +- uint32_t cp_hqd_pipe_priority; +- uint32_t cp_hqd_queue_priority; +- uint32_t cp_hqd_quantum; +- uint32_t cp_hqd_pq_base_lo; +- uint32_t cp_hqd_pq_base_hi; +- uint32_t cp_hqd_pq_rptr; +- uint32_t cp_hqd_pq_rptr_report_addr_lo; +- uint32_t cp_hqd_pq_rptr_report_addr_hi; +- uint32_t cp_hqd_pq_wptr_poll_addr_lo; +- uint32_t cp_hqd_pq_wptr_poll_addr_hi; +- uint32_t cp_hqd_pq_doorbell_control; +- uint32_t cp_hqd_pq_wptr; +- uint32_t cp_hqd_pq_control; +- uint32_t cp_hqd_ib_base_addr_lo; +- uint32_t cp_hqd_ib_base_addr_hi; +- uint32_t cp_hqd_ib_rptr; +- uint32_t cp_hqd_ib_control; +- uint32_t cp_hqd_iq_timer; +- uint32_t cp_hqd_iq_rptr; +- uint32_t cp_hqd_dequeue_request; +- uint32_t cp_hqd_dma_offload; +- uint32_t cp_hqd_sema_cmd; +- uint32_t cp_hqd_msg_type; +- uint32_t cp_hqd_atomic0_preop_lo; +- uint32_t cp_hqd_atomic0_preop_hi; +- uint32_t cp_hqd_atomic1_preop_lo; +- uint32_t cp_hqd_atomic1_preop_hi; +- uint32_t cp_hqd_hq_status0; +- uint32_t cp_hqd_hq_control0; +- uint32_t cp_mqd_control; +- uint32_t cp_hqd_hq_status1; +- uint32_t cp_hqd_hq_control1; +- uint32_t cp_hqd_eop_base_addr_lo; +- uint32_t cp_hqd_eop_base_addr_hi; +- uint32_t cp_hqd_eop_control; +- uint32_t cp_hqd_eop_rptr; +- uint32_t cp_hqd_eop_wptr; +- uint32_t cp_hqd_eop_done_events; +- uint32_t cp_hqd_ctx_save_base_addr_lo; +- uint32_t cp_hqd_ctx_save_base_addr_hi; +- uint32_t cp_hqd_ctx_save_control; +- uint32_t cp_hqd_cntl_stack_offset; +- uint32_t cp_hqd_cntl_stack_size; +- uint32_t cp_hqd_wg_state_offset; +- uint32_t cp_hqd_ctx_save_size; +- uint32_t cp_hqd_gds_resource_state; +- uint32_t cp_hqd_error; +- uint32_t cp_hqd_eop_wptr_mem; +- uint32_t cp_hqd_eop_dones; +- uint32_t reserved_182; +- uint32_t reserved_183; +- uint32_t reserved_184; +- uint32_t reserved_185; +- uint32_t reserved_186; +- uint32_t reserved_187; +- uint32_t reserved_188; +- uint32_t reserved_189; +- uint32_t reserved_190; +- uint32_t reserved_191; +- uint32_t iqtimer_pkt_header; +- uint32_t iqtimer_pkt_dw0; +- uint32_t iqtimer_pkt_dw1; +- uint32_t iqtimer_pkt_dw2; +- uint32_t iqtimer_pkt_dw3; +- uint32_t iqtimer_pkt_dw4; +- uint32_t iqtimer_pkt_dw5; +- uint32_t iqtimer_pkt_dw6; +- uint32_t iqtimer_pkt_dw7; +- uint32_t iqtimer_pkt_dw8; +- uint32_t iqtimer_pkt_dw9; +- uint32_t iqtimer_pkt_dw10; +- uint32_t iqtimer_pkt_dw11; +- uint32_t iqtimer_pkt_dw12; +- uint32_t iqtimer_pkt_dw13; +- uint32_t iqtimer_pkt_dw14; +- uint32_t iqtimer_pkt_dw15; +- uint32_t iqtimer_pkt_dw16; +- uint32_t iqtimer_pkt_dw17; +- uint32_t iqtimer_pkt_dw18; +- uint32_t iqtimer_pkt_dw19; +- uint32_t iqtimer_pkt_dw20; +- uint32_t iqtimer_pkt_dw21; +- uint32_t iqtimer_pkt_dw22; +- uint32_t iqtimer_pkt_dw23; +- uint32_t iqtimer_pkt_dw24; +- uint32_t iqtimer_pkt_dw25; +- uint32_t iqtimer_pkt_dw26; +- uint32_t iqtimer_pkt_dw27; +- uint32_t iqtimer_pkt_dw28; +- uint32_t iqtimer_pkt_dw29; +- uint32_t iqtimer_pkt_dw30; +- uint32_t iqtimer_pkt_dw31; +- uint32_t reserved_225; +- uint32_t reserved_226; +- uint32_t reserved_227; +- uint32_t set_resources_header; +- uint32_t set_resources_dw1; +- uint32_t set_resources_dw2; +- uint32_t set_resources_dw3; +- uint32_t set_resources_dw4; +- uint32_t set_resources_dw5; +- uint32_t set_resources_dw6; +- uint32_t set_resources_dw7; +- uint32_t reserved_236; +- uint32_t reserved_237; +- uint32_t reserved_238; +- uint32_t reserved_239; +- uint32_t queue_doorbell_id0; +- uint32_t queue_doorbell_id1; +- uint32_t queue_doorbell_id2; +- uint32_t queue_doorbell_id3; +- uint32_t queue_doorbell_id4; +- uint32_t queue_doorbell_id5; +- uint32_t queue_doorbell_id6; +- uint32_t queue_doorbell_id7; +- uint32_t queue_doorbell_id8; +- uint32_t queue_doorbell_id9; +- uint32_t queue_doorbell_id10; +- uint32_t queue_doorbell_id11; +- uint32_t queue_doorbell_id12; +- uint32_t queue_doorbell_id13; +- uint32_t queue_doorbell_id14; +- uint32_t queue_doorbell_id15; +-}; +- + struct vi_ce_ib_state { + uint32_t ce_ib_completion_status; + uint32_t ce_constegnine_count; +-- +2.7.4 + |