diff options
Diffstat (limited to 'meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/0014-drm-amdgpu-gfx8-apply-dynamic-cu-mask-to-APUs-as-wel.patch')
| -rw-r--r-- | meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/0014-drm-amdgpu-gfx8-apply-dynamic-cu-mask-to-APUs-as-wel.patch | 38 |
1 files changed, 38 insertions, 0 deletions
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/0014-drm-amdgpu-gfx8-apply-dynamic-cu-mask-to-APUs-as-wel.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/0014-drm-amdgpu-gfx8-apply-dynamic-cu-mask-to-APUs-as-wel.patch new file mode 100644 index 00000000..02745b47 --- /dev/null +++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/0014-drm-amdgpu-gfx8-apply-dynamic-cu-mask-to-APUs-as-wel.patch @@ -0,0 +1,38 @@ +From e0f47ef118faaeef1ae92ba7f481543f7039daf9 Mon Sep 17 00:00:00 2001 +From: Alex Deucher <alexander.deucher@amd.com> +Date: Thu, 24 Aug 2017 16:46:29 -0400 +Subject: [PATCH 0014/4131] drm/amdgpu/gfx8: apply dynamic cu mask to APUs as + well + +Confirmed with the hw team. It's the same for all asics. + +Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> +Signed-off-by: Alex Deucher <alexander.deucher@amd.com> +--- + drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 10 ++++------ + 1 file changed, 4 insertions(+), 6 deletions(-) + +diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c +index 656c419..0e21711 100644 +--- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c ++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c +@@ -4625,12 +4625,10 @@ static int gfx_v8_0_mqd_init(struct amdgpu_ring *ring) + mqd->compute_static_thread_mgmt_se2 = 0xffffffff; + mqd->compute_static_thread_mgmt_se3 = 0xffffffff; + mqd->compute_misc_reserved = 0x00000003; +- if (!(adev->flags & AMD_IS_APU)) { +- mqd->dynamic_cu_mask_addr_lo = lower_32_bits(ring->mqd_gpu_addr +- + offsetof(struct vi_mqd_allocation, dynamic_cu_mask)); +- mqd->dynamic_cu_mask_addr_hi = upper_32_bits(ring->mqd_gpu_addr +- + offsetof(struct vi_mqd_allocation, dynamic_cu_mask)); +- } ++ mqd->dynamic_cu_mask_addr_lo = lower_32_bits(ring->mqd_gpu_addr ++ + offsetof(struct vi_mqd_allocation, dynamic_cu_mask)); ++ mqd->dynamic_cu_mask_addr_hi = upper_32_bits(ring->mqd_gpu_addr ++ + offsetof(struct vi_mqd_allocation, dynamic_cu_mask)); + eop_base_addr = ring->eop_gpu_addr >> 8; + mqd->cp_hqd_eop_base_addr_lo = eop_base_addr; + mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr); +-- +2.7.4 + |