aboutsummaryrefslogtreecommitdiffstats
path: root/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71-e3000/0107-mmc-sdhci-Add-32-bit-block-count-support-for-v4-mode.patch
diff options
context:
space:
mode:
Diffstat (limited to 'meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71-e3000/0107-mmc-sdhci-Add-32-bit-block-count-support-for-v4-mode.patch')
-rw-r--r--meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71-e3000/0107-mmc-sdhci-Add-32-bit-block-count-support-for-v4-mode.patch79
1 files changed, 79 insertions, 0 deletions
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71-e3000/0107-mmc-sdhci-Add-32-bit-block-count-support-for-v4-mode.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71-e3000/0107-mmc-sdhci-Add-32-bit-block-count-support-for-v4-mode.patch
new file mode 100644
index 00000000..407c8917
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71-e3000/0107-mmc-sdhci-Add-32-bit-block-count-support-for-v4-mode.patch
@@ -0,0 +1,79 @@
+From 6f5130259bf48630d9bf77359e8f8e4badc55cfe Mon Sep 17 00:00:00 2001
+From: Sudheesh Mavila <sudheesh.mavila@amd.com>
+Date: Tue, 22 Jan 2019 23:00:26 +0530
+Subject: [PATCH 107/131] mmc: sdhci: Add 32-bit block count support for v4
+ mode
+
+Host Controller Version 4.10 re-defines SDMA System Address register
+as 32-bit Block Count for v4 mode, and SDMA uses ADMA System
+Address register (05Fh-058h) instead if v4 mode is enabled. Also
+when using 32-bit block count, 16-bit block count register need
+to be set to zero.
+
+Since using 32-bit Block Count would cause problems for auto-cmd23,
+it can be chosen via host->quirk2.
+
+Signed-off-by: Chunyan Zhang <zhang.chunyan@linaro.org>
+Acked-by: Adrian Hunter <adrian.hunter@intel.com>
+Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
+
+Signed-off-by: Sudheesh Mavila <sudheesh.mavila@amd.com>
+---
+ drivers/mmc/host/sdhci.c | 14 +++++++++++++-
+ drivers/mmc/host/sdhci.h | 8 ++++++++
+ 2 files changed, 21 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c
+index 4b18f3f..da59b0a 100644
+--- a/drivers/mmc/host/sdhci.c
++++ b/drivers/mmc/host/sdhci.c
+@@ -998,7 +998,19 @@ static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_command *cmd)
+ /* Set the DMA boundary value and block size */
+ sdhci_writew(host, SDHCI_MAKE_BLKSZ(host->sdma_boundary, data->blksz),
+ SDHCI_BLOCK_SIZE);
+- sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT);
++
++ /*
++ * For Version 4.10 onwards, if v4 mode is enabled, 32-bit Block Count
++ * can be supported, in that case 16-bit block count register must be 0.
++ */
++ if (host->version >= SDHCI_SPEC_410 && host->v4_mode &&
++ (host->quirks2 & SDHCI_QUIRK2_USE_32BIT_BLK_CNT)) {
++ if (sdhci_readw(host, SDHCI_BLOCK_COUNT))
++ sdhci_writew(host, 0, SDHCI_BLOCK_COUNT);
++ sdhci_writew(host, data->blocks, SDHCI_32BIT_BLK_CNT);
++ } else {
++ sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT);
++ }
+ }
+
+ static inline bool sdhci_auto_cmd12(struct sdhci_host *host,
+diff --git a/drivers/mmc/host/sdhci.h b/drivers/mmc/host/sdhci.h
+index 0b5ac1c..5197966 100755
+--- a/drivers/mmc/host/sdhci.h
++++ b/drivers/mmc/host/sdhci.h
+@@ -28,6 +28,7 @@
+
+ #define SDHCI_DMA_ADDRESS 0x00
+ #define SDHCI_ARGUMENT2 SDHCI_DMA_ADDRESS
++#define SDHCI_32BIT_BLK_CNT SDHCI_DMA_ADDRESS
+
+ #define SDHCI_BLOCK_SIZE 0x04
+ #define SDHCI_MAKE_BLKSZ(dma, blksz) (((dma & 0x7) << 12) | (blksz & 0xFFF))
+@@ -449,6 +450,13 @@ struct sdhci_host {
+ #define SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN (1<<15)
+ /* Controller has CRC in 136 bit Command Response */
+ #define SDHCI_QUIRK2_RSP_136_HAS_CRC (1<<16)
++/*
++ * 32-bit block count may not support eMMC where upper bits of CMD23 are used
++ * for other purposes. Consequently we support 16-bit block count by default.
++ * Otherwise, SDHCI_QUIRK2_USE_32BIT_BLK_CNT can be selected to use 32-bit
++ * block count.
++ */
++#define SDHCI_QUIRK2_USE_32BIT_BLK_CNT (1<<18)
+
+ int irq; /* Device IRQ */
+ void __iomem *ioaddr; /* Mapped address */
+--
+2.7.4
+