diff options
Diffstat (limited to 'common/recipes-kernel/linux/linux-yocto-4.9.21/0070-x86-speculation-Add-virtualized-speculative-store-by.patch')
| -rw-r--r-- | common/recipes-kernel/linux/linux-yocto-4.9.21/0070-x86-speculation-Add-virtualized-speculative-store-by.patch | 104 |
1 files changed, 0 insertions, 104 deletions
diff --git a/common/recipes-kernel/linux/linux-yocto-4.9.21/0070-x86-speculation-Add-virtualized-speculative-store-by.patch b/common/recipes-kernel/linux/linux-yocto-4.9.21/0070-x86-speculation-Add-virtualized-speculative-store-by.patch deleted file mode 100644 index f7f668b1..00000000 --- a/common/recipes-kernel/linux/linux-yocto-4.9.21/0070-x86-speculation-Add-virtualized-speculative-store-by.patch +++ /dev/null @@ -1,104 +0,0 @@ -From fa6ec76841319858ad2046107420a63feda4a0bb Mon Sep 17 00:00:00 2001 -From: Tom Lendacky <thomas.lendacky@amd.com> -Date: Thu, 17 May 2018 17:09:18 +0200 -Subject: [PATCH 70/93] x86/speculation: Add virtualized speculative store - bypass disable support - -commit 11fb0683493b2da112cd64c9dada221b52463bf7 upstream - -Some AMD processors only support a non-architectural means of enabling -speculative store bypass disable (SSBD). To allow a simplified view of -this to a guest, an architectural definition has been created through a new -CPUID bit, 0x80000008_EBX[25], and a new MSR, 0xc001011f. With this, a -hypervisor can virtualize the existence of this definition and provide an -architectural method for using SSBD to a guest. - -Add the new CPUID feature, the new MSR and update the existing SSBD -support to use this MSR when present. - -Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com> -Signed-off-by: Thomas Gleixner <tglx@linutronix.de> -Reviewed-by: Borislav Petkov <bp@suse.de> -Signed-off-by: David Woodhouse <dwmw@amazon.co.uk> -Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> ---- - arch/x86/include/asm/cpufeatures.h | 1 + - arch/x86/include/asm/msr-index.h | 2 ++ - arch/x86/kernel/cpu/bugs.c | 4 +++- - arch/x86/kernel/process.c | 13 ++++++++++++- - 4 files changed, 18 insertions(+), 2 deletions(-) - -diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h -index ec87b8c..c278f27 100644 ---- a/arch/x86/include/asm/cpufeatures.h -+++ b/arch/x86/include/asm/cpufeatures.h -@@ -274,6 +274,7 @@ - #define X86_FEATURE_AMD_IBPB (13*32+12) /* Indirect Branch Prediction Barrier */ - #define X86_FEATURE_AMD_IBRS (13*32+14) /* Indirect Branch Restricted Speculation */ - #define X86_FEATURE_AMD_STIBP (13*32+15) /* Single Thread Indirect Branch Predictors */ -+#define X86_FEATURE_VIRT_SSBD (13*32+25) /* Virtualized Speculative Store Bypass Disable */ - - /* Thermal and Power Management Leaf, CPUID level 0x00000006 (eax), word 14 */ - #define X86_FEATURE_DTHERM (14*32+ 0) /* Digital Thermal Sensor */ -diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h -index 0145a0b..ad5d0d8 100644 ---- a/arch/x86/include/asm/msr-index.h -+++ b/arch/x86/include/asm/msr-index.h -@@ -323,6 +323,8 @@ - #define MSR_AMD64_IBSOPDATA4 0xc001103d - #define MSR_AMD64_IBS_REG_COUNT_MAX 8 /* includes MSR_AMD64_IBSBRTARGET */ - -+#define MSR_AMD64_VIRT_SPEC_CTRL 0xc001011f -+ - /* Fam 17h MSRs */ - #define MSR_F17H_IRPERF 0xc00000e9 - -diff --git a/arch/x86/kernel/cpu/bugs.c b/arch/x86/kernel/cpu/bugs.c -index d00e246..97987b5 100644 ---- a/arch/x86/kernel/cpu/bugs.c -+++ b/arch/x86/kernel/cpu/bugs.c -@@ -204,7 +204,9 @@ static void x86_amd_ssb_disable(void) - { - u64 msrval = x86_amd_ls_cfg_base | x86_amd_ls_cfg_ssbd_mask; - -- if (boot_cpu_has(X86_FEATURE_LS_CFG_SSBD)) -+ if (boot_cpu_has(X86_FEATURE_VIRT_SSBD)) -+ wrmsrl(MSR_AMD64_VIRT_SPEC_CTRL, SPEC_CTRL_SSBD); -+ else if (boot_cpu_has(X86_FEATURE_LS_CFG_SSBD)) - wrmsrl(MSR_AMD64_LS_CFG, msrval); - } - -diff --git a/arch/x86/kernel/process.c b/arch/x86/kernel/process.c -index 1e9d155..6d9e1ee 100644 ---- a/arch/x86/kernel/process.c -+++ b/arch/x86/kernel/process.c -@@ -312,6 +312,15 @@ static __always_inline void amd_set_core_ssb_state(unsigned long tifn) - } - #endif - -+static __always_inline void amd_set_ssb_virt_state(unsigned long tifn) -+{ -+ /* -+ * SSBD has the same definition in SPEC_CTRL and VIRT_SPEC_CTRL, -+ * so ssbd_tif_to_spec_ctrl() just works. -+ */ -+ wrmsrl(MSR_AMD64_VIRT_SPEC_CTRL, ssbd_tif_to_spec_ctrl(tifn)); -+} -+ - static __always_inline void intel_set_ssb_state(unsigned long tifn) - { - u64 msr = x86_spec_ctrl_base | ssbd_tif_to_spec_ctrl(tifn); -@@ -321,7 +330,9 @@ static __always_inline void intel_set_ssb_state(unsigned long tifn) - - static __always_inline void __speculative_store_bypass_update(unsigned long tifn) - { -- if (static_cpu_has(X86_FEATURE_LS_CFG_SSBD)) -+ if (static_cpu_has(X86_FEATURE_VIRT_SSBD)) -+ amd_set_ssb_virt_state(tifn); -+ else if (static_cpu_has(X86_FEATURE_LS_CFG_SSBD)) - amd_set_core_ssb_state(tifn); - else - intel_set_ssb_state(tifn); --- -2.7.4 - |