diff options
Diffstat (limited to 'common/recipes-kernel/linux/linux-yocto-4.9.21/0056-x86-cpu-AMD-Make-LFENCE-a-serializing-instruction.patch')
| -rw-r--r-- | common/recipes-kernel/linux/linux-yocto-4.9.21/0056-x86-cpu-AMD-Make-LFENCE-a-serializing-instruction.patch | 70 |
1 files changed, 0 insertions, 70 deletions
diff --git a/common/recipes-kernel/linux/linux-yocto-4.9.21/0056-x86-cpu-AMD-Make-LFENCE-a-serializing-instruction.patch b/common/recipes-kernel/linux/linux-yocto-4.9.21/0056-x86-cpu-AMD-Make-LFENCE-a-serializing-instruction.patch deleted file mode 100644 index 188ff893..00000000 --- a/common/recipes-kernel/linux/linux-yocto-4.9.21/0056-x86-cpu-AMD-Make-LFENCE-a-serializing-instruction.patch +++ /dev/null @@ -1,70 +0,0 @@ -From 8f7353cbbd5a5a54c876c2be30217ba568e5989c Mon Sep 17 00:00:00 2001 -From: Tom Lendacky <thomas.lendacky@amd.com> -Date: Mon, 8 Jan 2018 16:09:21 -0600 -Subject: [PATCH 056/103] x86/cpu/AMD: Make LFENCE a serializing instruction - -commit e4d0e84e490790798691aaa0f2e598637f1867ec upstream. - -To aid in speculation control, make LFENCE a serializing instruction -since it has less overhead than MFENCE. This is done by setting bit 1 -of MSR 0xc0011029 (DE_CFG). Some families that support LFENCE do not -have this MSR. For these families, the LFENCE instruction is already -serializing. - -Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com> -Signed-off-by: Thomas Gleixner <tglx@linutronix.de> -Reviewed-by: Reviewed-by: Borislav Petkov <bp@suse.de> -Cc: Peter Zijlstra <peterz@infradead.org> -Cc: Tim Chen <tim.c.chen@linux.intel.com> -Cc: Dave Hansen <dave.hansen@intel.com> -Cc: Borislav Petkov <bp@alien8.de> -Cc: Dan Williams <dan.j.williams@intel.com> -Cc: Linus Torvalds <torvalds@linux-foundation.org> -Cc: Greg Kroah-Hartman <gregkh@linux-foundation.org> -Cc: David Woodhouse <dwmw@amazon.co.uk> -Cc: Paul Turner <pjt@google.com> -Link: https://lkml.kernel.org/r/20180108220921.12580.71694.stgit@tlendack-t1.amdoffice.net -Signed-off-by: Razvan Ghitulete <rga@amazon.de> -Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> ---- - arch/x86/include/asm/msr-index.h | 2 ++ - arch/x86/kernel/cpu/amd.c | 10 ++++++++++ - 2 files changed, 12 insertions(+) - -diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h -index 78f3760..b1c0969 100644 ---- a/arch/x86/include/asm/msr-index.h -+++ b/arch/x86/include/asm/msr-index.h -@@ -330,6 +330,8 @@ - #define FAM10H_MMIO_CONF_BASE_MASK 0xfffffffULL - #define FAM10H_MMIO_CONF_BASE_SHIFT 20 - #define MSR_FAM10H_NODE_ID 0xc001100c -+#define MSR_F10H_DECFG 0xc0011029 -+#define MSR_F10H_DECFG_LFENCE_SERIALIZE_BIT 1 - - /* K8 MSRs */ - #define MSR_K8_TOP_MEM1 0xc001001a -diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c -index 2b4cf04..8b5b19d 100644 ---- a/arch/x86/kernel/cpu/amd.c -+++ b/arch/x86/kernel/cpu/amd.c -@@ -782,6 +782,16 @@ static void init_amd(struct cpuinfo_x86 *c) - set_cpu_cap(c, X86_FEATURE_K8); - - if (cpu_has(c, X86_FEATURE_XMM2)) { -+ /* -+ * A serializing LFENCE has less overhead than MFENCE, so -+ * use it for execution serialization. On families which -+ * don't have that MSR, LFENCE is already serializing. -+ * msr_set_bit() uses the safe accessors, too, even if the MSR -+ * is not present. -+ */ -+ msr_set_bit(MSR_F10H_DECFG, -+ MSR_F10H_DECFG_LFENCE_SERIALIZE_BIT); -+ - /* MFENCE stops RDTSC speculation */ - set_cpu_cap(c, X86_FEATURE_MFENCE_RDTSC); - } --- -2.7.4 - |