diff options
Diffstat (limited to 'common/recipes-kernel/linux/linux-yocto-4.9.21/0005-x86-cpufeatures-Add-Intel-PCONFIG-cpufeature.patch')
| -rw-r--r-- | common/recipes-kernel/linux/linux-yocto-4.9.21/0005-x86-cpufeatures-Add-Intel-PCONFIG-cpufeature.patch | 39 |
1 files changed, 0 insertions, 39 deletions
diff --git a/common/recipes-kernel/linux/linux-yocto-4.9.21/0005-x86-cpufeatures-Add-Intel-PCONFIG-cpufeature.patch b/common/recipes-kernel/linux/linux-yocto-4.9.21/0005-x86-cpufeatures-Add-Intel-PCONFIG-cpufeature.patch deleted file mode 100644 index 1e33e521..00000000 --- a/common/recipes-kernel/linux/linux-yocto-4.9.21/0005-x86-cpufeatures-Add-Intel-PCONFIG-cpufeature.patch +++ /dev/null @@ -1,39 +0,0 @@ -From a3032e35007a8178f448e471acb6bc6c972c087a Mon Sep 17 00:00:00 2001 -From: "Kirill A. Shutemov" <kirill.shutemov@linux.intel.com> -Date: Mon, 5 Mar 2018 19:25:51 +0300 -Subject: [PATCH 05/93] x86/cpufeatures: Add Intel PCONFIG cpufeature - -commit 7958b2246fadf54b7ff820a2a5a2c5ca1554716f upstream. - -CPUID.0x7.0x0:EDX[18] indicates whether Intel CPU support PCONFIG instruction. - -Signed-off-by: Kirill A. Shutemov <kirill.shutemov@linux.intel.com> -Cc: Dave Hansen <dave.hansen@intel.com> -Cc: Kai Huang <kai.huang@linux.intel.com> -Cc: Linus Torvalds <torvalds@linux-foundation.org> -Cc: Peter Zijlstra <peterz@infradead.org> -Cc: Thomas Gleixner <tglx@linutronix.de> -Cc: Tom Lendacky <thomas.lendacky@amd.com> -Cc: linux-mm@kvack.org -Link: http://lkml.kernel.org/r/20180305162610.37510-4-kirill.shutemov@linux.intel.com -Signed-off-by: Ingo Molnar <mingo@kernel.org> -Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> ---- - arch/x86/include/asm/cpufeatures.h | 1 + - 1 file changed, 1 insertion(+) - -diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h -index ed7a1d2..a248531 100644 ---- a/arch/x86/include/asm/cpufeatures.h -+++ b/arch/x86/include/asm/cpufeatures.h -@@ -302,6 +302,7 @@ - /* Intel-defined CPU features, CPUID level 0x00000007:0 (EDX), word 18 */ - #define X86_FEATURE_AVX512_4VNNIW (18*32+ 2) /* AVX-512 Neural Network Instructions */ - #define X86_FEATURE_AVX512_4FMAPS (18*32+ 3) /* AVX-512 Multiply Accumulation Single precision */ -+#define X86_FEATURE_PCONFIG (18*32+18) /* Intel PCONFIG */ - #define X86_FEATURE_SPEC_CTRL (18*32+26) /* "" Speculation Control (IBRS + IBPB) */ - #define X86_FEATURE_INTEL_STIBP (18*32+27) /* "" Single Thread Indirect Branch Predictors */ - #define X86_FEATURE_ARCH_CAPABILITIES (18*32+29) /* IA32_ARCH_CAPABILITIES MSR (Intel) */ --- -2.7.4 - |