aboutsummaryrefslogtreecommitdiffstats
path: root/common/recipes-kernel/linux/linux-yocto-4.19.8/1770-drm-amd-display-Expose-support-for-NV12-on-suitable-.patch
diff options
context:
space:
mode:
Diffstat (limited to 'common/recipes-kernel/linux/linux-yocto-4.19.8/1770-drm-amd-display-Expose-support-for-NV12-on-suitable-.patch')
-rw-r--r--common/recipes-kernel/linux/linux-yocto-4.19.8/1770-drm-amd-display-Expose-support-for-NV12-on-suitable-.patch144
1 files changed, 144 insertions, 0 deletions
diff --git a/common/recipes-kernel/linux/linux-yocto-4.19.8/1770-drm-amd-display-Expose-support-for-NV12-on-suitable-.patch b/common/recipes-kernel/linux/linux-yocto-4.19.8/1770-drm-amd-display-Expose-support-for-NV12-on-suitable-.patch
new file mode 100644
index 00000000..4dae1f44
--- /dev/null
+++ b/common/recipes-kernel/linux/linux-yocto-4.19.8/1770-drm-amd-display-Expose-support-for-NV12-on-suitable-.patch
@@ -0,0 +1,144 @@
+From 9d1deedb92223fc5d78ac17b53ca4d70d0b7cc69 Mon Sep 17 00:00:00 2001
+From: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
+Date: Fri, 15 Mar 2019 15:45:34 -0400
+Subject: [PATCH 1770/2940] drm/amd/display: Expose support for NV12 on
+ suitable planes
+
+[Why]
+Hardware can support video surfaces and DC tells us which planes are
+suitable via DC plane caps.
+
+[How]
+The supported formats array will now vary based on what DC tells us,
+so create an array and fill it dynamically based on plane types and
+caps.
+
+Ideally we'd query support for every format via DC plane caps, but for
+the framework is in place to do so later with this.
+
+Change-Id: Ic80f12d3f7e95fc33219f90e95219468f044ac6d
+Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
+Reviewed-by: Sun peng Li <Sunpeng.Li@amd.com>
+Acked-by: Bhawanpreet Lakha <Bhawanpreet Lakha@amd.com>
+---
+ .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 86 ++++++++++++-------
+ 1 file changed, 55 insertions(+), 31 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+index d30d834c13cb..f0d17628213e 100644
+--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
++++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+@@ -4235,46 +4235,71 @@ static const u32 cursor_formats[] = {
+ DRM_FORMAT_ARGB8888
+ };
+
+-static int amdgpu_dm_plane_init(struct amdgpu_display_manager *dm,
+- struct drm_plane *plane,
+- unsigned long possible_crtcs,
+- const struct dc_plane_cap *plane_cap)
++static int get_plane_formats(const struct drm_plane *plane,
++ const struct dc_plane_cap *plane_cap,
++ uint32_t *formats, int max_formats)
+ {
+- int res = -EPERM;
++ int i, num_formats = 0;
++
++ /*
++ * TODO: Query support for each group of formats directly from
++ * DC plane caps. This will require adding more formats to the
++ * caps list.
++ */
+
+ switch (plane->type) {
+ case DRM_PLANE_TYPE_PRIMARY:
+- res = drm_universal_plane_init(
+- dm->adev->ddev,
+- plane,
+- possible_crtcs,
+- &dm_plane_funcs,
+- rgb_formats,
+- ARRAY_SIZE(rgb_formats),
+- NULL, plane->type, NULL);
++ for (i = 0; i < ARRAY_SIZE(rgb_formats); ++i) {
++ if (num_formats >= max_formats)
++ break;
++
++ formats[num_formats++] = rgb_formats[i];
++ }
++
++ if (plane_cap && plane_cap->supports_nv12)
++ formats[num_formats++] = DRM_FORMAT_NV12;
+ break;
++
+ case DRM_PLANE_TYPE_OVERLAY:
+- res = drm_universal_plane_init(
+- dm->adev->ddev,
+- plane,
+- possible_crtcs,
+- &dm_plane_funcs,
+- overlay_formats,
+- ARRAY_SIZE(overlay_formats),
+- NULL, plane->type, NULL);
++ for (i = 0; i < ARRAY_SIZE(overlay_formats); ++i) {
++ if (num_formats >= max_formats)
++ break;
++
++ formats[num_formats++] = overlay_formats[i];
++ }
+ break;
++
+ case DRM_PLANE_TYPE_CURSOR:
+- res = drm_universal_plane_init(
+- dm->adev->ddev,
+- plane,
+- possible_crtcs,
+- &dm_plane_funcs,
+- cursor_formats,
+- ARRAY_SIZE(cursor_formats),
+- NULL, plane->type, NULL);
++ for (i = 0; i < ARRAY_SIZE(cursor_formats); ++i) {
++ if (num_formats >= max_formats)
++ break;
++
++ formats[num_formats++] = cursor_formats[i];
++ }
+ break;
+ }
+
++ return num_formats;
++}
++
++static int amdgpu_dm_plane_init(struct amdgpu_display_manager *dm,
++ struct drm_plane *plane,
++ unsigned long possible_crtcs,
++ const struct dc_plane_cap *plane_cap)
++{
++ uint32_t formats[32];
++ int num_formats;
++ int res = -EPERM;
++
++ num_formats = get_plane_formats(plane, plane_cap, formats,
++ ARRAY_SIZE(formats));
++
++ res = drm_universal_plane_init(dm->adev->ddev, plane, possible_crtcs,
++ &dm_plane_funcs, formats, num_formats,
++ NULL, plane->type, NULL);
++ if (res)
++ return res;
++
+ if (plane->type == DRM_PLANE_TYPE_OVERLAY &&
+ plane_cap && plane_cap->per_pixel_alpha) {
+ unsigned int blend_caps = BIT(DRM_MODE_BLEND_PIXEL_NONE) |
+@@ -4290,8 +4315,7 @@ static int amdgpu_dm_plane_init(struct amdgpu_display_manager *dm,
+ if (plane->funcs->reset)
+ plane->funcs->reset(plane);
+
+-
+- return res;
++ return 0;
+ }
+
+ static int amdgpu_dm_crtc_init(struct amdgpu_display_manager *dm,
+--
+2.17.1
+