diff options
Diffstat (limited to 'common/recipes-kernel/linux/linux-yocto-4.19.8/1763-drm-amd-display-extending-AUX-SW-Timeout.patch')
| -rw-r--r-- | common/recipes-kernel/linux/linux-yocto-4.19.8/1763-drm-amd-display-extending-AUX-SW-Timeout.patch | 72 |
1 files changed, 72 insertions, 0 deletions
diff --git a/common/recipes-kernel/linux/linux-yocto-4.19.8/1763-drm-amd-display-extending-AUX-SW-Timeout.patch b/common/recipes-kernel/linux/linux-yocto-4.19.8/1763-drm-amd-display-extending-AUX-SW-Timeout.patch new file mode 100644 index 00000000..40b73c3b --- /dev/null +++ b/common/recipes-kernel/linux/linux-yocto-4.19.8/1763-drm-amd-display-extending-AUX-SW-Timeout.patch @@ -0,0 +1,72 @@ +From 3d4a1b5460287a8feb16342c4ef39a5e97ec1c01 Mon Sep 17 00:00:00 2001 +From: Martin Leung <martin.leung@amd.com> +Date: Tue, 26 Mar 2019 13:14:11 -0400 +Subject: [PATCH 1763/2940] drm/amd/display: extending AUX SW Timeout + +[Why] +AUX takes longer to reply when using active DP-DVI dongle on some asics +resulting in up to 2000+ us edid read (timeout). + +[How] +1. Adjust AUX poll to match spec +2. Extend the SW timeout. This does not affect normal +operation since we exit the loop as soon as AUX acks. + +Signed-off-by: Martin Leung <martin.leung@amd.com> +Reviewed-by: Jun Lei <Jun.Lei@amd.com> +Acked-by: Joshua Aberback <Joshua.Aberback@amd.com> +Acked-by: Leo Li <sunpeng.li@amd.com> +--- + drivers/gpu/drm/amd/display/dc/dce/dce_aux.c | 9 ++++++--- + drivers/gpu/drm/amd/display/dc/dce/dce_aux.h | 6 +++--- + 2 files changed, 9 insertions(+), 6 deletions(-) + +diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c b/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c +index 937b5cffd7ef..bd33c47183fc 100644 +--- a/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c ++++ b/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c +@@ -190,6 +190,12 @@ static void submit_channel_request( + AUXP_IMPCAL_OVERRIDE_ENABLE, 1, + AUXP_IMPCAL_OVERRIDE_ENABLE, 0); + } ++ ++ REG_UPDATE(AUX_INTERRUPT_CONTROL, AUX_SW_DONE_ACK, 1); ++ ++ REG_WAIT(AUX_SW_STATUS, AUX_SW_DONE, 0, ++ 10, aux110->timeout_period/10); ++ + /* set the delay and the number of bytes to write */ + + /* The length include +@@ -242,9 +248,6 @@ static void submit_channel_request( + } + } + +- REG_UPDATE(AUX_INTERRUPT_CONTROL, AUX_SW_DONE_ACK, 1); +- REG_WAIT(AUX_SW_STATUS, AUX_SW_DONE, 0, +- 10, aux110->timeout_period/10); + REG_UPDATE(AUX_SW_CONTROL, AUX_SW_GO, 1); + } + +diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_aux.h b/drivers/gpu/drm/amd/display/dc/dce/dce_aux.h +index aab5f0c34584..ce6a26d189b0 100644 +--- a/drivers/gpu/drm/amd/display/dc/dce/dce_aux.h ++++ b/drivers/gpu/drm/amd/display/dc/dce/dce_aux.h +@@ -71,11 +71,11 @@ enum { /* This is the timeout as defined in DP 1.2a, + * at most within ~240usec. That means, + * increasing this timeout will not affect normal operation, + * and we'll timeout after +- * SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD = 1600usec. ++ * SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD = 2400usec. + * This timeout is especially important for +- * resume from S3 and CTS. ++ * converters, resume from S3, and CTS. + */ +- SW_AUX_TIMEOUT_PERIOD_MULTIPLIER = 4 ++ SW_AUX_TIMEOUT_PERIOD_MULTIPLIER = 6 + }; + + struct dce_aux { +-- +2.17.1 + |