diff options
Diffstat (limited to 'common/recipes-kernel/linux/linux-yocto-4.19.8/1761-drm-amd-display-Pass-plane-caps-into-amdgpu_dm_plane.patch')
| -rw-r--r-- | common/recipes-kernel/linux/linux-yocto-4.19.8/1761-drm-amd-display-Pass-plane-caps-into-amdgpu_dm_plane.patch | 170 |
1 files changed, 170 insertions, 0 deletions
diff --git a/common/recipes-kernel/linux/linux-yocto-4.19.8/1761-drm-amd-display-Pass-plane-caps-into-amdgpu_dm_plane.patch b/common/recipes-kernel/linux/linux-yocto-4.19.8/1761-drm-amd-display-Pass-plane-caps-into-amdgpu_dm_plane.patch new file mode 100644 index 00000000..f5a061b9 --- /dev/null +++ b/common/recipes-kernel/linux/linux-yocto-4.19.8/1761-drm-amd-display-Pass-plane-caps-into-amdgpu_dm_plane.patch @@ -0,0 +1,170 @@ +From 9278f817342f05826347ca33d6670a86ec7c8f70 Mon Sep 17 00:00:00 2001 +From: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> +Date: Thu, 14 Mar 2019 15:58:51 -0400 +Subject: [PATCH 1761/2940] drm/amd/display: Pass plane caps into + amdgpu_dm_plane_init + +[Why] +When deciding to add properties or expose formats on DRM planes we +should be querying the caps for the DC plane it's supposed to represent. + +[How] +Pass plane caps down into plane initialization, refactoring overlay +plane initialization to have the overlay plane be represented by +the first overlay capable DC plane. + +Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> +Reviewed-by: Leo Li <sunpeng.li@amd.com> +Signed-off-by: Chaudhary Amit Kumar <Chaudharyamit.Kumar@amd.com> +--- + .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 64 ++++++++++--------- + 1 file changed, 34 insertions(+), 30 deletions(-) + +diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +index 80a8cddd3db7..d30d834c13cb 100644 +--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c ++++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +@@ -104,7 +104,8 @@ amdgpu_dm_update_connector_after_detect(struct amdgpu_dm_connector *aconnector); + + static int amdgpu_dm_plane_init(struct amdgpu_display_manager *dm, + struct drm_plane *plane, +- unsigned long possible_crtcs); ++ unsigned long possible_crtcs, ++ const struct dc_plane_cap *plane_cap); + static int amdgpu_dm_crtc_init(struct amdgpu_display_manager *dm, + struct drm_plane *plane, + uint32_t link_index); +@@ -1961,7 +1962,8 @@ amdgpu_dm_register_backlight_device(struct amdgpu_display_manager *dm) + + static int initialize_plane(struct amdgpu_display_manager *dm, + struct amdgpu_mode_info *mode_info, int plane_id, +- enum drm_plane_type plane_type) ++ enum drm_plane_type plane_type, ++ const struct dc_plane_cap *plane_cap) + { + struct drm_plane *plane; + unsigned long possible_crtcs; +@@ -1985,7 +1987,7 @@ static int initialize_plane(struct amdgpu_display_manager *dm, + if (plane_id >= dm->dc->caps.max_streams) + possible_crtcs = 0xff; + +- ret = amdgpu_dm_plane_init(dm, plane, possible_crtcs); ++ ret = amdgpu_dm_plane_init(dm, plane, possible_crtcs, plane_cap); + + if (ret) { + DRM_ERROR("KMS: Failed to initialize plane\n"); +@@ -2038,8 +2040,9 @@ static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev) + struct amdgpu_encoder *aencoder = NULL; + struct amdgpu_mode_info *mode_info = &adev->mode_info; + uint32_t link_cnt; +- int32_t overlay_planes, primary_planes; ++ int32_t primary_planes; + enum dc_connection_type new_connection_type = dc_connection_none; ++ const struct dc_plane_cap *plane; + + link_cnt = dm->dc->caps.max_links; + if (amdgpu_dm_mode_config_init(dm->adev)) { +@@ -2047,24 +2050,6 @@ static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev) + return -EINVAL; + } + +- /* +- * Determine the number of overlay planes supported. +- * Only support DCN for now, and cap so we don't encourage +- * userspace to use up all the planes. +- */ +- overlay_planes = 0; +- +- for (i = 0; i < dm->dc->caps.max_planes; ++i) { +- struct dc_plane_cap *plane = &dm->dc->caps.planes[i]; +- +- if (plane->type == DC_PLANE_TYPE_DCN_UNIVERSAL && +- plane->blends_with_above && plane->blends_with_below && +- plane->supports_argb8888) +- overlay_planes += 1; +- } +- +- overlay_planes = min(overlay_planes, 1); +- + /* There is one primary plane per CRTC */ + primary_planes = dm->dc->caps.max_streams; + ASSERT(primary_planes <= AMDGPU_MAX_PLANES); +@@ -2074,9 +2059,10 @@ static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev) + * Order is reversed to match iteration order in atomic check. + */ + for (i = (primary_planes - 1); i >= 0; i--) { +- if (initialize_plane(dm, mode_info, i, +- DRM_PLANE_TYPE_PRIMARY)) { ++ plane = &dm->dc->caps.planes[i]; + ++ if (initialize_plane(dm, mode_info, i, ++ DRM_PLANE_TYPE_PRIMARY, plane)) { + DRM_ERROR("KMS: Failed to initialize primary plane\n"); + goto fail; + } +@@ -2087,13 +2073,30 @@ static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev) + * These planes have a higher DRM index than the primary planes since + * they should be considered as having a higher z-order. + * Order is reversed to match iteration order in atomic check. ++ * ++ * Only support DCN for now, and only expose one so we don't encourage ++ * userspace to use up all the pipes. + */ +- for (i = (overlay_planes - 1); i >= 0; i--) { ++ for (i = 0; i < dm->dc->caps.max_planes; ++i) { ++ struct dc_plane_cap *plane = &dm->dc->caps.planes[i]; ++ ++ if (plane->type != DC_PLANE_TYPE_DCN_UNIVERSAL) ++ continue; ++ ++ if (!plane->blends_with_above || !plane->blends_with_below) ++ continue; ++ ++ if (!plane->supports_argb8888) ++ continue; ++ + if (initialize_plane(dm, NULL, primary_planes + i, +- DRM_PLANE_TYPE_OVERLAY)) { ++ DRM_PLANE_TYPE_OVERLAY, plane)) { + DRM_ERROR("KMS: Failed to initialize overlay plane\n"); + goto fail; + } ++ ++ /* Only create one overlay plane. */ ++ break; + } + + for (i = 0; i < dm->dc->caps.max_streams; i++) +@@ -4234,7 +4237,8 @@ static const u32 cursor_formats[] = { + + static int amdgpu_dm_plane_init(struct amdgpu_display_manager *dm, + struct drm_plane *plane, +- unsigned long possible_crtcs) ++ unsigned long possible_crtcs, ++ const struct dc_plane_cap *plane_cap) + { + int res = -EPERM; + +@@ -4271,8 +4275,8 @@ static int amdgpu_dm_plane_init(struct amdgpu_display_manager *dm, + break; + } + +- /* TODO: Check DC plane caps explicitly here for adding propertes */ +- if (plane->type == DRM_PLANE_TYPE_OVERLAY) { ++ if (plane->type == DRM_PLANE_TYPE_OVERLAY && ++ plane_cap && plane_cap->per_pixel_alpha) { + unsigned int blend_caps = BIT(DRM_MODE_BLEND_PIXEL_NONE) | + BIT(DRM_MODE_BLEND_PREMULTI); + +@@ -4304,7 +4308,7 @@ static int amdgpu_dm_crtc_init(struct amdgpu_display_manager *dm, + goto fail; + + cursor_plane->type = DRM_PLANE_TYPE_CURSOR; +- res = amdgpu_dm_plane_init(dm, cursor_plane, 0); ++ res = amdgpu_dm_plane_init(dm, cursor_plane, 0, NULL); + + acrtc = kzalloc(sizeof(struct amdgpu_crtc), GFP_KERNEL); + if (!acrtc) +-- +2.17.1 + |