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Diffstat (limited to 'common/recipes-kernel/linux/linux-yocto-4.19.8/1707-drm-amdgpu-Correct-the-irq-types-num-of-sdma.patch')
-rw-r--r--common/recipes-kernel/linux/linux-yocto-4.19.8/1707-drm-amdgpu-Correct-the-irq-types-num-of-sdma.patch254
1 files changed, 254 insertions, 0 deletions
diff --git a/common/recipes-kernel/linux/linux-yocto-4.19.8/1707-drm-amdgpu-Correct-the-irq-types-num-of-sdma.patch b/common/recipes-kernel/linux/linux-yocto-4.19.8/1707-drm-amdgpu-Correct-the-irq-types-num-of-sdma.patch
new file mode 100644
index 00000000..14e75b84
--- /dev/null
+++ b/common/recipes-kernel/linux/linux-yocto-4.19.8/1707-drm-amdgpu-Correct-the-irq-types-num-of-sdma.patch
@@ -0,0 +1,254 @@
+From d20e7571617d37381ce70f3892b11b2aad3fbb85 Mon Sep 17 00:00:00 2001
+From: Emily Deng <Emily.Deng@amd.com>
+Date: Thu, 28 Mar 2019 17:29:10 +0800
+Subject: [PATCH 1707/2940] drm/amdgpu: Correct the irq types' num of sdma
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Fix the issue about TDR-2 will have "fallback timer expired on ring sdma1".
+It is because the wrong number of irq types setting.
+
+Signed-off-by: Emily Deng <Emily.Deng@amd.com>
+Reviewed-by: Christian König <christian.koenig@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.h | 7 ++-----
+ drivers/gpu/drm/amd/amdgpu/cik_sdma.c | 8 ++++----
+ drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c | 8 ++++----
+ drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c | 8 ++++----
+ drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 25 ++++++++++++------------
+ drivers/gpu/drm/amd/amdgpu/si_dma.c | 8 ++++----
+ 6 files changed, 30 insertions(+), 34 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.h
+index e988c3f09ecc..b0d81aa9557e 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.h
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.h
+@@ -28,11 +28,8 @@
+ #define AMDGPU_MAX_SDMA_INSTANCES 2
+
+ enum amdgpu_sdma_irq {
+- AMDGPU_SDMA_IRQ_TRAP0 = 0,
+- AMDGPU_SDMA_IRQ_TRAP1,
+- AMDGPU_SDMA_IRQ_ECC0,
+- AMDGPU_SDMA_IRQ_ECC1,
+-
++ AMDGPU_SDMA_IRQ_INSTANCE0 = 0,
++ AMDGPU_SDMA_IRQ_INSTANCE1,
+ AMDGPU_SDMA_IRQ_LAST
+ };
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
+index 7842116aea95..978ad9045ff7 100644
+--- a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
++++ b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
+@@ -977,8 +977,8 @@ static int cik_sdma_sw_init(void *handle)
+ r = amdgpu_ring_init(adev, ring, 1024,
+ &adev->sdma.trap_irq,
+ (i == 0) ?
+- AMDGPU_SDMA_IRQ_TRAP0 :
+- AMDGPU_SDMA_IRQ_TRAP1);
++ AMDGPU_SDMA_IRQ_INSTANCE0 :
++ AMDGPU_SDMA_IRQ_INSTANCE1);
+ if (r)
+ return r;
+ }
+@@ -1114,7 +1114,7 @@ static int cik_sdma_set_trap_irq_state(struct amdgpu_device *adev,
+ u32 sdma_cntl;
+
+ switch (type) {
+- case AMDGPU_SDMA_IRQ_TRAP0:
++ case AMDGPU_SDMA_IRQ_INSTANCE0:
+ switch (state) {
+ case AMDGPU_IRQ_STATE_DISABLE:
+ sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET);
+@@ -1130,7 +1130,7 @@ static int cik_sdma_set_trap_irq_state(struct amdgpu_device *adev,
+ break;
+ }
+ break;
+- case AMDGPU_SDMA_IRQ_TRAP1:
++ case AMDGPU_SDMA_IRQ_INSTANCE1:
+ switch (state) {
+ case AMDGPU_IRQ_STATE_DISABLE:
+ sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET);
+diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
+index e9dfc55a7809..112acd8eff83 100644
+--- a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
++++ b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
+@@ -870,8 +870,8 @@ static int sdma_v2_4_sw_init(void *handle)
+ r = amdgpu_ring_init(adev, ring, 1024,
+ &adev->sdma.trap_irq,
+ (i == 0) ?
+- AMDGPU_SDMA_IRQ_TRAP0 :
+- AMDGPU_SDMA_IRQ_TRAP1);
++ AMDGPU_SDMA_IRQ_INSTANCE0 :
++ AMDGPU_SDMA_IRQ_INSTANCE1);
+ if (r)
+ return r;
+ }
+@@ -1006,7 +1006,7 @@ static int sdma_v2_4_set_trap_irq_state(struct amdgpu_device *adev,
+ u32 sdma_cntl;
+
+ switch (type) {
+- case AMDGPU_SDMA_IRQ_TRAP0:
++ case AMDGPU_SDMA_IRQ_INSTANCE0:
+ switch (state) {
+ case AMDGPU_IRQ_STATE_DISABLE:
+ sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET);
+@@ -1022,7 +1022,7 @@ static int sdma_v2_4_set_trap_irq_state(struct amdgpu_device *adev,
+ break;
+ }
+ break;
+- case AMDGPU_SDMA_IRQ_TRAP1:
++ case AMDGPU_SDMA_IRQ_INSTANCE1:
+ switch (state) {
+ case AMDGPU_IRQ_STATE_DISABLE:
+ sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET);
+diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
+index d3c8a4b16db0..fd6f6e15f271 100644
+--- a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
+@@ -1154,8 +1154,8 @@ static int sdma_v3_0_sw_init(void *handle)
+ r = amdgpu_ring_init(adev, ring, 1024,
+ &adev->sdma.trap_irq,
+ (i == 0) ?
+- AMDGPU_SDMA_IRQ_TRAP0 :
+- AMDGPU_SDMA_IRQ_TRAP1);
++ AMDGPU_SDMA_IRQ_INSTANCE0 :
++ AMDGPU_SDMA_IRQ_INSTANCE1);
+ if (r)
+ return r;
+ }
+@@ -1340,7 +1340,7 @@ static int sdma_v3_0_set_trap_irq_state(struct amdgpu_device *adev,
+ u32 sdma_cntl;
+
+ switch (type) {
+- case AMDGPU_SDMA_IRQ_TRAP0:
++ case AMDGPU_SDMA_IRQ_INSTANCE0:
+ switch (state) {
+ case AMDGPU_IRQ_STATE_DISABLE:
+ sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET);
+@@ -1356,7 +1356,7 @@ static int sdma_v3_0_set_trap_irq_state(struct amdgpu_device *adev,
+ break;
+ }
+ break;
+- case AMDGPU_SDMA_IRQ_TRAP1:
++ case AMDGPU_SDMA_IRQ_INSTANCE1:
+ switch (state) {
+ case AMDGPU_IRQ_STATE_DISABLE:
+ sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET);
+diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
+index 59ba47dc5692..1fa8087c5a7e 100644
+--- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
+@@ -1553,13 +1553,13 @@ static int sdma_v4_0_late_init(void *handle)
+ if (r)
+ goto sysfs;
+ resume:
+- r = amdgpu_irq_get(adev, &adev->sdma.ecc_irq, AMDGPU_SDMA_IRQ_ECC0);
++ r = amdgpu_irq_get(adev, &adev->sdma.ecc_irq, AMDGPU_SDMA_IRQ_INSTANCE0);
+ if (r)
+ goto irq;
+
+- r = amdgpu_irq_get(adev, &adev->sdma.ecc_irq, AMDGPU_SDMA_IRQ_ECC1);
++ r = amdgpu_irq_get(adev, &adev->sdma.ecc_irq, AMDGPU_SDMA_IRQ_INSTANCE1);
+ if (r) {
+- amdgpu_irq_put(adev, &adev->sdma.ecc_irq, AMDGPU_SDMA_IRQ_ECC0);
++ amdgpu_irq_put(adev, &adev->sdma.ecc_irq, AMDGPU_SDMA_IRQ_INSTANCE0);
+ goto irq;
+ }
+
+@@ -1623,8 +1623,8 @@ static int sdma_v4_0_sw_init(void *handle)
+ r = amdgpu_ring_init(adev, ring, 1024,
+ &adev->sdma.trap_irq,
+ (i == 0) ?
+- AMDGPU_SDMA_IRQ_TRAP0 :
+- AMDGPU_SDMA_IRQ_TRAP1);
++ AMDGPU_SDMA_IRQ_INSTANCE0 :
++ AMDGPU_SDMA_IRQ_INSTANCE1);
+ if (r)
+ return r;
+
+@@ -1643,8 +1643,8 @@ static int sdma_v4_0_sw_init(void *handle)
+ r = amdgpu_ring_init(adev, ring, 1024,
+ &adev->sdma.trap_irq,
+ (i == 0) ?
+- AMDGPU_SDMA_IRQ_TRAP0 :
+- AMDGPU_SDMA_IRQ_TRAP1);
++ AMDGPU_SDMA_IRQ_INSTANCE0 :
++ AMDGPU_SDMA_IRQ_INSTANCE1);
+ if (r)
+ return r;
+ }
+@@ -1711,8 +1711,8 @@ static int sdma_v4_0_hw_fini(void *handle)
+ if (amdgpu_sriov_vf(adev))
+ return 0;
+
+- amdgpu_irq_put(adev, &adev->sdma.ecc_irq, AMDGPU_SDMA_IRQ_ECC0);
+- amdgpu_irq_put(adev, &adev->sdma.ecc_irq, AMDGPU_SDMA_IRQ_ECC1);
++ amdgpu_irq_put(adev, &adev->sdma.ecc_irq, AMDGPU_SDMA_IRQ_INSTANCE0);
++ amdgpu_irq_put(adev, &adev->sdma.ecc_irq, AMDGPU_SDMA_IRQ_INSTANCE1);
+
+ sdma_v4_0_ctx_switch_enable(adev, false);
+ sdma_v4_0_enable(adev, false);
+@@ -1782,13 +1782,12 @@ static int sdma_v4_0_set_trap_irq_state(struct amdgpu_device *adev,
+ unsigned type,
+ enum amdgpu_interrupt_state state)
+ {
+- unsigned int instance = (type == AMDGPU_SDMA_IRQ_TRAP0) ? 0 : 1;
+ u32 sdma_cntl;
+
+- sdma_cntl = RREG32_SDMA(instance, mmSDMA0_CNTL);
++ sdma_cntl = RREG32_SDMA(type, mmSDMA0_CNTL);
+ sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE,
+ state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
+- WREG32_SDMA(instance, mmSDMA0_CNTL, sdma_cntl);
++ WREG32_SDMA(type, mmSDMA0_CNTL, sdma_cntl);
+
+ return 0;
+ }
+@@ -1908,7 +1907,7 @@ static int sdma_v4_0_set_ecc_irq_state(struct amdgpu_device *adev,
+ {
+ u32 sdma_edc_config;
+
+- u32 reg_offset = (type == AMDGPU_SDMA_IRQ_ECC0) ?
++ u32 reg_offset = (type == AMDGPU_SDMA_IRQ_INSTANCE0) ?
+ sdma_v4_0_get_reg_offset(adev, 0, mmSDMA0_EDC_CONFIG) :
+ sdma_v4_0_get_reg_offset(adev, 1, mmSDMA0_EDC_CONFIG);
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/si_dma.c b/drivers/gpu/drm/amd/amdgpu/si_dma.c
+index f15f196684ba..3eeefd40dae0 100644
+--- a/drivers/gpu/drm/amd/amdgpu/si_dma.c
++++ b/drivers/gpu/drm/amd/amdgpu/si_dma.c
+@@ -503,8 +503,8 @@ static int si_dma_sw_init(void *handle)
+ r = amdgpu_ring_init(adev, ring, 1024,
+ &adev->sdma.trap_irq,
+ (i == 0) ?
+- AMDGPU_SDMA_IRQ_TRAP0 :
+- AMDGPU_SDMA_IRQ_TRAP1);
++ AMDGPU_SDMA_IRQ_INSTANCE0 :
++ AMDGPU_SDMA_IRQ_INSTANCE1);
+ if (r)
+ return r;
+ }
+@@ -591,7 +591,7 @@ static int si_dma_set_trap_irq_state(struct amdgpu_device *adev,
+ u32 sdma_cntl;
+
+ switch (type) {
+- case AMDGPU_SDMA_IRQ_TRAP0:
++ case AMDGPU_SDMA_IRQ_INSTANCE0:
+ switch (state) {
+ case AMDGPU_IRQ_STATE_DISABLE:
+ sdma_cntl = RREG32(DMA_CNTL + DMA0_REGISTER_OFFSET);
+@@ -607,7 +607,7 @@ static int si_dma_set_trap_irq_state(struct amdgpu_device *adev,
+ break;
+ }
+ break;
+- case AMDGPU_SDMA_IRQ_TRAP1:
++ case AMDGPU_SDMA_IRQ_INSTANCE1:
+ switch (state) {
+ case AMDGPU_IRQ_STATE_DISABLE:
+ sdma_cntl = RREG32(DMA_CNTL + DMA1_REGISTER_OFFSET);
+--
+2.17.1
+
generated by cgit 1.2.3-korg (git 2.39.0) at 2024-04-19 00:27:15 +0000