diff options
Diffstat (limited to 'common/recipes-kernel/linux/linux-yocto-4.19.8/1704-drm-amd-display-Populate-macro_tile_size-field-for-d.patch')
| -rw-r--r-- | common/recipes-kernel/linux/linux-yocto-4.19.8/1704-drm-amd-display-Populate-macro_tile_size-field-for-d.patch | 138 |
1 files changed, 138 insertions, 0 deletions
diff --git a/common/recipes-kernel/linux/linux-yocto-4.19.8/1704-drm-amd-display-Populate-macro_tile_size-field-for-d.patch b/common/recipes-kernel/linux/linux-yocto-4.19.8/1704-drm-amd-display-Populate-macro_tile_size-field-for-d.patch new file mode 100644 index 00000000..ffad1967 --- /dev/null +++ b/common/recipes-kernel/linux/linux-yocto-4.19.8/1704-drm-amd-display-Populate-macro_tile_size-field-for-d.patch @@ -0,0 +1,138 @@ +From dd00d7995df6fad8b133a146f181f2e0eb467065 Mon Sep 17 00:00:00 2001 +From: Joshua Aberback <joshua.aberback@amd.com> +Date: Mon, 18 Mar 2019 13:40:47 -0400 +Subject: [PATCH 1704/2940] drm/amd/display: Populate macro_tile_size field for + dml + +Create a functions to return swizzle types for dml + +Change-Id: Ieaeb9ce26568ee1ebdb4d2d5ce9a17af07e56c54 +Signed-off-by: Joshua Aberback <joshua.aberback@amd.com> +Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> +Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> +--- + .../gpu/drm/amd/display/dc/calcs/dcn_calcs.c | 88 ++++++++++--------- + .../gpu/drm/amd/display/dc/inc/dcn_calcs.h | 2 + + 2 files changed, 50 insertions(+), 40 deletions(-) + +diff --git a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c +index e572ac59b035..8843361e842d 100644 +--- a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c ++++ b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c +@@ -247,6 +247,53 @@ static enum dcn_bw_defs tl_pixel_format_to_bw_defs(enum surface_pixel_format for + } + } + ++enum source_macro_tile_size swizzle_mode_to_macro_tile_size(enum swizzle_mode_values sw_mode) ++{ ++ switch (sw_mode) { ++ /* for 4/8/16 high tiles */ ++ case DC_SW_LINEAR: ++ return dm_4k_tile; ++ case DC_SW_4KB_S: ++ case DC_SW_4KB_S_X: ++ return dm_4k_tile; ++ case DC_SW_64KB_S: ++ case DC_SW_64KB_S_X: ++ case DC_SW_64KB_S_T: ++ return dm_64k_tile; ++ case DC_SW_VAR_S: ++ case DC_SW_VAR_S_X: ++ return dm_256k_tile; ++ ++ /* For 64bpp 2 high tiles */ ++ case DC_SW_4KB_D: ++ case DC_SW_4KB_D_X: ++ return dm_4k_tile; ++ case DC_SW_64KB_D: ++ case DC_SW_64KB_D_X: ++ case DC_SW_64KB_D_T: ++ return dm_64k_tile; ++ case DC_SW_VAR_D: ++ case DC_SW_VAR_D_X: ++ return dm_256k_tile; ++ ++ case DC_SW_4KB_R: ++ case DC_SW_4KB_R_X: ++ return dm_4k_tile; ++ case DC_SW_64KB_R: ++ case DC_SW_64KB_R_X: ++ return dm_64k_tile; ++ case DC_SW_VAR_R: ++ case DC_SW_VAR_R_X: ++ return dm_256k_tile; ++ ++ /* Unsupported swizzle modes for dcn */ ++ case DC_SW_256B_S: ++ default: ++ ASSERT(0); /* Not supported */ ++ return 0; ++ } ++} ++ + static void pipe_ctx_to_e2e_pipe_params ( + const struct pipe_ctx *pipe, + struct _vcs_dpi_display_pipe_params_st *input) +@@ -287,46 +334,7 @@ static void pipe_ctx_to_e2e_pipe_params ( + input->src.cur0_src_width = 128; /* TODO: Cursor calcs, not curently stored */ + input->src.cur0_bpp = 32; + +- switch (pipe->plane_state->tiling_info.gfx9.swizzle) { +- /* for 4/8/16 high tiles */ +- case DC_SW_LINEAR: +- input->src.macro_tile_size = dm_4k_tile; +- break; +- case DC_SW_4KB_S: +- case DC_SW_4KB_S_X: +- input->src.macro_tile_size = dm_4k_tile; +- break; +- case DC_SW_64KB_S: +- case DC_SW_64KB_S_X: +- case DC_SW_64KB_S_T: +- input->src.macro_tile_size = dm_64k_tile; +- break; +- case DC_SW_VAR_S: +- case DC_SW_VAR_S_X: +- input->src.macro_tile_size = dm_256k_tile; +- break; +- +- /* For 64bpp 2 high tiles */ +- case DC_SW_4KB_D: +- case DC_SW_4KB_D_X: +- input->src.macro_tile_size = dm_4k_tile; +- break; +- case DC_SW_64KB_D: +- case DC_SW_64KB_D_X: +- case DC_SW_64KB_D_T: +- input->src.macro_tile_size = dm_64k_tile; +- break; +- case DC_SW_VAR_D: +- case DC_SW_VAR_D_X: +- input->src.macro_tile_size = dm_256k_tile; +- break; +- +- /* Unsupported swizzle modes for dcn */ +- case DC_SW_256B_S: +- default: +- ASSERT(0); /* Not supported */ +- break; +- } ++ input->src.macro_tile_size = swizzle_mode_to_macro_tile_size(pipe->plane_state->tiling_info.gfx9.swizzle); + + switch (pipe->plane_state->rotation) { + case ROTATION_ANGLE_0: +diff --git a/drivers/gpu/drm/amd/display/dc/inc/dcn_calcs.h b/drivers/gpu/drm/amd/display/dc/inc/dcn_calcs.h +index ece954a40a8e..86ec3f69c765 100644 +--- a/drivers/gpu/drm/amd/display/dc/inc/dcn_calcs.h ++++ b/drivers/gpu/drm/amd/display/dc/inc/dcn_calcs.h +@@ -631,5 +631,7 @@ void dcn_bw_update_from_pplib(struct dc *dc); + void dcn_bw_notify_pplib_of_wm_ranges(struct dc *dc); + void dcn_bw_sync_calcs_and_dml(struct dc *dc); + ++enum source_macro_tile_size swizzle_mode_to_macro_tile_size(enum swizzle_mode_values sw_mode); ++ + #endif /* __DCN_CALCS_H__ */ + +-- +2.17.1 + |