diff options
Diffstat (limited to 'common/recipes-kernel/linux/linux-yocto-4.19.8/1698-drm-amd-display-Clean-up-old-pplib-interface-functio.patch')
| -rw-r--r-- | common/recipes-kernel/linux/linux-yocto-4.19.8/1698-drm-amd-display-Clean-up-old-pplib-interface-functio.patch | 127 |
1 files changed, 127 insertions, 0 deletions
diff --git a/common/recipes-kernel/linux/linux-yocto-4.19.8/1698-drm-amd-display-Clean-up-old-pplib-interface-functio.patch b/common/recipes-kernel/linux/linux-yocto-4.19.8/1698-drm-amd-display-Clean-up-old-pplib-interface-functio.patch new file mode 100644 index 00000000..114d96c0 --- /dev/null +++ b/common/recipes-kernel/linux/linux-yocto-4.19.8/1698-drm-amd-display-Clean-up-old-pplib-interface-functio.patch @@ -0,0 +1,127 @@ +From fe613a403537699252cfcdaa35175a514e5be73a Mon Sep 17 00:00:00 2001 +From: Fatemeh Darbehani <fatemeh.darbehani@amd.com> +Date: Tue, 12 Mar 2019 13:57:36 -0400 +Subject: [PATCH 1698/2940] drm/amd/display: Clean up old pplib interface + functions + +[Why] +set_display_requirement, dcn1_pplib_apply_display_requirements +are no longer used and should be removed. + +Change-Id: Ie4d61d873d2f3ef2d5587fbc0b38079bdcf93ceb +Signed-off-by: Fatemeh Darbehani <fatemeh.darbehani@amd.com> +Reviewed-by: Hersen Wu <hersenxs.wu@amd.com> +Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> +--- + .../amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c | 25 ------------------- + .../drm/amd/display/dc/dcn10/dcn10_clk_mgr.c | 17 ------------- + .../drm/amd/display/dc/dcn10/dcn10_clk_mgr.h | 4 --- + drivers/gpu/drm/amd/display/dc/dm_pp_smu.h | 6 ----- + 4 files changed, 52 deletions(-) + +diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c +index dc0bc544d26c..905b28198352 100644 +--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c ++++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c +@@ -509,30 +509,6 @@ bool dm_pp_get_static_clocks( + return true; + } + +-void pp_rv_set_display_requirement(struct pp_smu *pp, +- struct pp_smu_display_requirement_rv *req) +-{ +- const struct dc_context *ctx = pp->dm; +- struct amdgpu_device *adev = ctx->driver_context; +- void *pp_handle = adev->powerplay.pp_handle; +- const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; +- struct pp_display_clock_request clock = {0}; +- +- clock.clock_type = amd_pp_dcf_clock; +- clock.clock_freq_in_khz = req->hard_min_dcefclk_mhz * 1000; +- if (pp_funcs && pp_funcs->display_clock_voltage_request) +- pp_funcs->display_clock_voltage_request(pp_handle, &clock); +- else if (adev->smu.funcs && adev->smu.funcs->display_clock_voltage_request) +- smu_display_clock_voltage_request(&adev->smu, &clock); +- +- clock.clock_type = amd_pp_f_clock; +- clock.clock_freq_in_khz = req->hard_min_fclk_mhz *1000; +- if (pp_funcs && pp_funcs->display_clock_voltage_request) +- pp_funcs->display_clock_voltage_request(pp_handle, &clock); +- else if (adev->smu.funcs && adev->smu.funcs->display_clock_voltage_request) +- smu_display_clock_voltage_request(&adev->smu, &clock); +-} +- + void pp_rv_set_wm_ranges(struct pp_smu *pp, + struct pp_smu_wm_range_sets *ranges) + { +@@ -659,7 +635,6 @@ void dm_pp_get_funcs( + struct pp_smu_funcs *funcs) + { + funcs->rv_funcs.pp_smu.dm = ctx; +- funcs->rv_funcs.set_display_requirement = pp_rv_set_display_requirement; + funcs->rv_funcs.set_wm_ranges = pp_rv_set_wm_ranges; + funcs->rv_funcs.set_pme_wa_enable = pp_rv_set_pme_wa_enable; + funcs->rv_funcs.set_display_count = pp_rv_set_active_display_count; +diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_clk_mgr.c +index d98ac7d90e4c..6ef480df84ce 100644 +--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_clk_mgr.c ++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_clk_mgr.c +@@ -43,23 +43,6 @@ + #define DC_LOGGER \ + clk_mgr->ctx->logger + +-void dcn1_pplib_apply_display_requirements( +- struct dc *dc, +- struct dc_state *context) +-{ +- struct dm_pp_display_configuration *pp_display_cfg = &context->pp_display_cfg; +- +- pp_display_cfg->min_engine_clock_khz = dc->res_pool->clk_mgr->clks.dcfclk_khz; +- pp_display_cfg->min_memory_clock_khz = dc->res_pool->clk_mgr->clks.fclk_khz; +- pp_display_cfg->min_engine_clock_deep_sleep_khz = dc->res_pool->clk_mgr->clks.dcfclk_deep_sleep_khz; +- pp_display_cfg->min_dcfc_deep_sleep_clock_khz = dc->res_pool->clk_mgr->clks.dcfclk_deep_sleep_khz; +- pp_display_cfg->min_dcfclock_khz = dc->res_pool->clk_mgr->clks.dcfclk_khz; +- pp_display_cfg->disp_clk_khz = dc->res_pool->clk_mgr->clks.dispclk_khz; +- dce110_fill_display_configs(context, pp_display_cfg); +- +- dm_pp_apply_display_requirements(dc->ctx, pp_display_cfg); +-} +- + static int dcn1_determine_dppclk_threshold(struct clk_mgr *clk_mgr, struct dc_clocks *new_clocks) + { + bool request_dpp_div = new_clocks->dispclk_khz > new_clocks->dppclk_khz; +diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_clk_mgr.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_clk_mgr.h +index a995eda443a3..97007cf33665 100644 +--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_clk_mgr.h ++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_clk_mgr.h +@@ -34,10 +34,6 @@ struct clk_bypass { + uint32_t dprefclk_bypass; + }; + +-void dcn1_pplib_apply_display_requirements( +- struct dc *dc, +- struct dc_state *context); +- + struct clk_mgr *dcn1_clk_mgr_create(struct dc_context *ctx); + + #endif //__DCN10_CLK_MGR_H__ +diff --git a/drivers/gpu/drm/amd/display/dc/dm_pp_smu.h b/drivers/gpu/drm/amd/display/dc/dm_pp_smu.h +index fe78f32819ed..b9bb8ef06cd8 100644 +--- a/drivers/gpu/drm/amd/display/dc/dm_pp_smu.h ++++ b/drivers/gpu/drm/amd/display/dc/dm_pp_smu.h +@@ -133,12 +133,6 @@ struct pp_smu_funcs_rv { + /* PME w/a */ + void (*set_pme_wa_enable)(struct pp_smu *pp); + +- /* +- * Legacy functions. Used for backwards comp. with existing +- * PPlib code. +- */ +- void (*set_display_requirement)(struct pp_smu *pp, +- struct pp_smu_display_requirement_rv *req); + }; + + struct pp_smu_funcs { +-- +2.17.1 + |