diff options
Diffstat (limited to 'common/recipes-kernel/linux/linux-yocto-4.19.8/1690-drm-amd-powerplay-fix-possible-hang-with-3-4K-monito.patch')
| -rw-r--r-- | common/recipes-kernel/linux/linux-yocto-4.19.8/1690-drm-amd-powerplay-fix-possible-hang-with-3-4K-monito.patch | 53 |
1 files changed, 53 insertions, 0 deletions
diff --git a/common/recipes-kernel/linux/linux-yocto-4.19.8/1690-drm-amd-powerplay-fix-possible-hang-with-3-4K-monito.patch b/common/recipes-kernel/linux/linux-yocto-4.19.8/1690-drm-amd-powerplay-fix-possible-hang-with-3-4K-monito.patch new file mode 100644 index 00000000..3771be1d --- /dev/null +++ b/common/recipes-kernel/linux/linux-yocto-4.19.8/1690-drm-amd-powerplay-fix-possible-hang-with-3-4K-monito.patch @@ -0,0 +1,53 @@ +From 82fdcbd5f0021d7fe2013490355e120c0c55039b Mon Sep 17 00:00:00 2001 +From: Evan Quan <evan.quan@amd.com> +Date: Tue, 26 Mar 2019 17:57:53 +0800 +Subject: [PATCH 1690/2940] drm/amd/powerplay: fix possible hang with 3+ 4K + monitors + +If DAL requires to force MCLK high, the FCLK will be +forced to high also. + +Change-Id: Iaff8956ca1faafaf904f0bec108f566e8bbf6a64 +Signed-off-by: Evan Quan <evan.quan@amd.com> +Acked-by: Alex Deucher <alexander.deucher@amd.com> +--- + drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c | 10 +++++++++- + 1 file changed, 9 insertions(+), 1 deletion(-) + +diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c +index 8168ed26607d..70dc641bf94d 100644 +--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c ++++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c +@@ -3479,6 +3479,7 @@ static int vega20_apply_clocks_adjust_rules(struct pp_hwmgr *hwmgr) + struct vega20_single_dpm_table *dpm_table; + bool vblank_too_short = false; + bool disable_mclk_switching; ++ bool disable_fclk_switching; + uint32_t i, latency; + + disable_mclk_switching = ((1 < hwmgr->display_config->num_display) && +@@ -3554,13 +3555,20 @@ static int vega20_apply_clocks_adjust_rules(struct pp_hwmgr *hwmgr) + if (hwmgr->display_config->nb_pstate_switch_disable) + dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value; + ++ if ((disable_mclk_switching && ++ (dpm_table->dpm_state.hard_min_level == dpm_table->dpm_levels[dpm_table->count - 1].value)) || ++ hwmgr->display_config->min_mem_set_clock / 100 >= dpm_table->dpm_levels[dpm_table->count - 1].value) ++ disable_fclk_switching = true; ++ else ++ disable_fclk_switching = false; ++ + /* fclk */ + dpm_table = &(data->dpm_table.fclk_table); + dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value; + dpm_table->dpm_state.soft_max_level = VG20_CLOCK_MAX_DEFAULT; + dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[0].value; + dpm_table->dpm_state.hard_max_level = VG20_CLOCK_MAX_DEFAULT; +- if (hwmgr->display_config->nb_pstate_switch_disable) ++ if (hwmgr->display_config->nb_pstate_switch_disable || disable_fclk_switching) + dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value; + + /* vclk */ +-- +2.17.1 + |