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Diffstat (limited to 'common/recipes-kernel/linux/linux-yocto-4.19.8/1643-drm-amd-display-cache-additional-dpcd-caps-for-HDR-c.patch')
-rw-r--r--common/recipes-kernel/linux/linux-yocto-4.19.8/1643-drm-amd-display-cache-additional-dpcd-caps-for-HDR-c.patch147
1 files changed, 147 insertions, 0 deletions
diff --git a/common/recipes-kernel/linux/linux-yocto-4.19.8/1643-drm-amd-display-cache-additional-dpcd-caps-for-HDR-c.patch b/common/recipes-kernel/linux/linux-yocto-4.19.8/1643-drm-amd-display-cache-additional-dpcd-caps-for-HDR-c.patch
new file mode 100644
index 00000000..303f54ea
--- /dev/null
+++ b/common/recipes-kernel/linux/linux-yocto-4.19.8/1643-drm-amd-display-cache-additional-dpcd-caps-for-HDR-c.patch
@@ -0,0 +1,147 @@
+From d5379d5bcc2061410cfafbf915ac52827b956a4e Mon Sep 17 00:00:00 2001
+From: Harmanprit Tatla <Harmanprit.Tatla@amd.com>
+Date: Fri, 1 Mar 2019 11:47:35 -0500
+Subject: [PATCH 1643/2940] drm/amd/display: cache additional dpcd caps for HDR
+ capability check
+
+[Why]
+Currently we are missing a few checks to see if HDR10 is allowed.
+In particular we never check for the extended colorimetry bit (whether its
+present or set to 1). Further we don't read in the dpcd block in DC that
+would provide these bits.
+
+[How]
+- Added in DC code to read in the block containing the extended colorimetry
+bit.
+
+Signed-off-by: Harmanprit Tatla <Harmanprit.Tatla@amd.com>
+Reviewed-by: Anthony Koo <Anthony.Koo@amd.com>
+Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+---
+ .../gpu/drm/amd/display/dc/core/dc_link_dp.c | 37 +++++++++++++++++--
+ drivers/gpu/drm/amd/display/dc/dc.h | 2 +
+ drivers/gpu/drm/amd/display/dc/dc_dp_types.h | 16 +++++++-
+ 3 files changed, 50 insertions(+), 5 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+index e1081e2dffdc..ef603f24c71c 100644
+--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
++++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+@@ -2418,6 +2418,10 @@ static bool retrieve_link_cap(struct dc_link *link)
+ {
+ uint8_t dpcd_data[DP_ADAPTER_CAP - DP_DPCD_REV + 1];
+
++ /*Only need to read 1 byte starting from DP_DPRX_FEATURE_ENUMERATION_LIST.
++ */
++ uint8_t dpcd_dprx_data = '\0';
++
+ struct dp_device_vendor_id sink_id;
+ union down_stream_port_count down_strm_port_count;
+ union edp_configuration_cap edp_config_cap;
+@@ -2454,7 +2458,10 @@ static bool retrieve_link_cap(struct dc_link *link)
+ aux_rd_interval.raw =
+ dpcd_data[DP_TRAINING_AUX_RD_INTERVAL];
+
+- if (aux_rd_interval.bits.EXT_RECIEVER_CAP_FIELD_PRESENT == 1) {
++ link->dpcd_caps.ext_receiver_cap_field_present =
++ aux_rd_interval.bits.EXT_RECEIVER_CAP_FIELD_PRESENT == 1 ? true:false;
++
++ if (aux_rd_interval.bits.EXT_RECEIVER_CAP_FIELD_PRESENT == 1) {
+ uint8_t ext_cap_data[16];
+
+ memset(ext_cap_data, '\0', sizeof(ext_cap_data));
+@@ -2474,6 +2481,31 @@ static bool retrieve_link_cap(struct dc_link *link)
+ }
+ }
+
++ link->dpcd_caps.dpcd_rev.raw =
++ dpcd_data[DP_DPCD_REV - DP_DPCD_REV];
++
++ if (link->dpcd_caps.dpcd_rev.raw >= 0x14) {
++ for (i = 0; i < read_dpcd_retry_cnt; i++) {
++ status = core_link_read_dpcd(
++ link,
++ DP_DPRX_FEATURE_ENUMERATION_LIST,
++ &dpcd_dprx_data,
++ sizeof(dpcd_dprx_data));
++ if (status == DC_OK)
++ break;
++ }
++
++ link->dpcd_caps.dprx_feature.raw = dpcd_dprx_data;
++
++ if (status != DC_OK)
++ dm_error("%s: Read DPRX caps data failed.\n", __func__);
++ }
++
++ else {
++ link->dpcd_caps.dprx_feature.raw = 0;
++ }
++
++
+ /* Error condition checking...
+ * It is impossible for Sink to report Max Lane Count = 0.
+ * It is possible for Sink to report Max Link Rate = 0, if it is
+@@ -2483,9 +2515,6 @@ static bool retrieve_link_cap(struct dc_link *link)
+ if (dpcd_data[DP_MAX_LANE_COUNT - DP_DPCD_REV] == 0)
+ return false;
+
+- link->dpcd_caps.dpcd_rev.raw =
+- dpcd_data[DP_DPCD_REV - DP_DPCD_REV];
+-
+ ds_port.byte = dpcd_data[DP_DOWNSTREAMPORT_PRESENT -
+ DP_DPCD_REV];
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
+index 17f6d0f0ba91..583b45b122d8 100644
+--- a/drivers/gpu/drm/amd/display/dc/dc.h
++++ b/drivers/gpu/drm/amd/display/dc/dc.h
+@@ -695,6 +695,7 @@ struct dpcd_caps {
+ union dpcd_rev dpcd_rev;
+ union max_lane_count max_ln_count;
+ union max_down_spread max_down_spread;
++ union dprx_feature dprx_feature;
+
+ /* valid only for eDP v1.4 or higher*/
+ uint8_t edp_supported_link_rates_count;
+@@ -721,6 +722,7 @@ struct dpcd_caps {
+ bool allow_invalid_MSA_timing_param;
+ bool panel_mode_edp;
+ bool dpcd_display_control_capable;
++ bool ext_receiver_cap_field_present;
+ };
+
+ #include "dc_link.h"
+diff --git a/drivers/gpu/drm/amd/display/dc/dc_dp_types.h b/drivers/gpu/drm/amd/display/dc/dc_dp_types.h
+index ec403cd8b834..11c68a399267 100644
+--- a/drivers/gpu/drm/amd/display/dc/dc_dp_types.h
++++ b/drivers/gpu/drm/amd/display/dc/dc_dp_types.h
+@@ -422,10 +422,24 @@ union edp_configuration_cap {
+ uint8_t raw;
+ };
+
++union dprx_feature {
++ struct {
++ uint8_t GTC_CAP:1; // bit 0: DP 1.3+
++ uint8_t SST_SPLIT_SDP_CAP:1; // bit 1: DP 1.4
++ uint8_t AV_SYNC_CAP:1; // bit 2: DP 1.3+
++ uint8_t VSC_SDP_COLORIMETRY_SUPPORTED:1; // bit 3: DP 1.3+
++ uint8_t VSC_EXT_VESA_SDP_SUPPORTED:1; // bit 4: DP 1.4
++ uint8_t VSC_EXT_VESA_SDP_CHAINING_SUPPORTED:1; // bit 5: DP 1.4
++ uint8_t VSC_EXT_CEA_SDP_SUPPORTED:1; // bit 6: DP 1.4
++ uint8_t VSC_EXT_CEA_SDP_CHAINING_SUPPORTED:1; // bit 7: DP 1.4
++ } bits;
++ uint8_t raw;
++};
++
+ union training_aux_rd_interval {
+ struct {
+ uint8_t TRAINIG_AUX_RD_INTERVAL:7;
+- uint8_t EXT_RECIEVER_CAP_FIELD_PRESENT:1;
++ uint8_t EXT_RECEIVER_CAP_FIELD_PRESENT:1;
+ } bits;
+ uint8_t raw;
+ };
+--
+2.17.1
+