diff options
Diffstat (limited to 'common/recipes-kernel/linux/linux-yocto-4.19.8/1637-drm-amd-display-fix-DP-422-VID_M-half-the-rate-issue.patch')
| -rw-r--r-- | common/recipes-kernel/linux/linux-yocto-4.19.8/1637-drm-amd-display-fix-DP-422-VID_M-half-the-rate-issue.patch | 133 |
1 files changed, 133 insertions, 0 deletions
diff --git a/common/recipes-kernel/linux/linux-yocto-4.19.8/1637-drm-amd-display-fix-DP-422-VID_M-half-the-rate-issue.patch b/common/recipes-kernel/linux/linux-yocto-4.19.8/1637-drm-amd-display-fix-DP-422-VID_M-half-the-rate-issue.patch new file mode 100644 index 00000000..e99702a4 --- /dev/null +++ b/common/recipes-kernel/linux/linux-yocto-4.19.8/1637-drm-amd-display-fix-DP-422-VID_M-half-the-rate-issue.patch @@ -0,0 +1,133 @@ +From 3d3de15bbc7292bcfa7595ed777566ecca9643be Mon Sep 17 00:00:00 2001 +From: Charlene Liu <charlene.liu@amd.com> +Date: Fri, 1 Mar 2019 11:12:50 -0500 +Subject: [PATCH 1637/2940] drm/amd/display: fix DP 422 VID_M half the rate + issue. + +[Description] +when programming VID_TIMING, we were using the original VESA timing for DP_VIDM/N. +for YCbCr420 or compressed YCbCr422, using half rate as YCbCr444. + +Change-Id: I8a60e252383c11f81789f190fd3477cb3083554b +Signed-off-by: Charlene Liu <charlene.liu@amd.com> +Reviewed-by: Nikola Cornij <Nikola.Cornij@amd.com> +Acked-by: Leo Li <sunpeng.li@amd.com> +--- + .../amd/display/dc/dce/dce_stream_encoder.c | 2 +- + .../display/dc/dce110/dce110_hw_sequencer.c | 3 +-- + .../amd/display/dc/dcn10/dcn10_hw_sequencer.c | 25 ++++++++++++++++++- + .../display/dc/dcn10/dcn10_stream_encoder.c | 7 +++--- + .../amd/display/dc/inc/hw/stream_encoder.h | 3 +-- + 5 files changed, 31 insertions(+), 9 deletions(-) + +diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c b/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c +index c60f4078c4c7..c5bb8db76a93 100644 +--- a/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c ++++ b/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c +@@ -977,7 +977,7 @@ static void dce110_stream_encoder_dp_unblank( + + uint64_t m_vid_l = n_vid; + +- m_vid_l *= param->pixel_clk_khz; ++ m_vid_l *= param->timing.pix_clk_100hz / 10; + m_vid_l = div_u64(m_vid_l, + param->link_settings.link_rate + * LINK_RATE_REF_FREQ_IN_KHZ); +diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c +index cc85a82e4417..1f09543b6d0e 100644 +--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c ++++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c +@@ -1052,9 +1052,8 @@ void dce110_unblank_stream(struct pipe_ctx *pipe_ctx, + struct dc_link *link = stream->link; + + /* only 3 items below are used by unblank */ +- params.pixel_clk_khz = pipe_ctx->stream->timing.pix_clk_100hz / 10; ++ params.timing = pipe_ctx->stream->timing; + params.link_settings.link_rate = link_settings->link_rate; +- params.pixel_encoding = pipe_ctx->stream->timing.pixel_encoding; + + if (dc_is_dp_signal(pipe_ctx->stream->signal)) + pipe_ctx->stream_res.stream_enc->funcs->dp_unblank(pipe_ctx->stream_res.stream_enc, ¶ms); +diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c +index d0014ab16a06..d46b29e0f02d 100644 +--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c ++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c +@@ -2899,6 +2899,29 @@ static void dcn10_setup_vupdate_interrupt(struct pipe_ctx *pipe_ctx) + tg->funcs->setup_vertical_interrupt2(tg, start_line); + } + ++static void dcn10_unblank_stream(struct pipe_ctx *pipe_ctx, ++ struct dc_link_settings *link_settings) ++{ ++ struct encoder_unblank_param params = { { 0 } }; ++ struct dc_stream_state *stream = pipe_ctx->stream; ++ struct dc_link *link = stream->link; ++ ++ /* only 3 items below are used by unblank */ ++ params.timing = pipe_ctx->stream->timing; ++ ++ params.link_settings.link_rate = link_settings->link_rate; ++ ++ if (dc_is_dp_signal(pipe_ctx->stream->signal)) { ++ if (params.timing.pixel_encoding == PIXEL_ENCODING_YCBCR420) ++ params.timing.pix_clk_100hz /= 2; ++ pipe_ctx->stream_res.stream_enc->funcs->dp_unblank(pipe_ctx->stream_res.stream_enc, ¶ms); ++ } ++ ++ if (link->local_sink && link->local_sink->sink_signal == SIGNAL_TYPE_EDP) { ++ link->dc->hwss.edp_backlight_control(link, true); ++ } ++} ++ + static const struct hw_sequencer_funcs dcn10_funcs = { + .program_gamut_remap = program_gamut_remap, + .init_hw = dcn10_init_hw, +@@ -2920,7 +2943,7 @@ static const struct hw_sequencer_funcs dcn10_funcs = { + .update_info_frame = dce110_update_info_frame, + .enable_stream = dce110_enable_stream, + .disable_stream = dce110_disable_stream, +- .unblank_stream = dce110_unblank_stream, ++ .unblank_stream = dcn10_unblank_stream, + .blank_stream = dce110_blank_stream, + .enable_audio_stream = dce110_enable_audio_stream, + .disable_audio_stream = dce110_disable_audio_stream, +diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c +index d2a15d2e9561..0d46aa75361b 100644 +--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c ++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c +@@ -836,14 +836,15 @@ void enc1_stream_encoder_dp_unblank( + uint64_t m_vid_l = n_vid; + + /* YCbCr 4:2:0 : Computed VID_M will be 2X the input rate */ +- if (param->pixel_encoding == PIXEL_ENCODING_YCBCR420) ++ if (param->timing.pixel_encoding == PIXEL_ENCODING_YCBCR420) { ++ /*this param->pixel_clk_khz is half of 444 rate for 420 already*/ + n_multiply = 1; +- ++ } + /* M / N = Fstream / Flink + * m_vid / n_vid = pixel rate / link rate + */ + +- m_vid_l *= param->pixel_clk_khz; ++ m_vid_l *= param->timing.pix_clk_100hz / 10; + m_vid_l = div_u64(m_vid_l, + param->link_settings.link_rate + * LINK_RATE_REF_FREQ_IN_KHZ); +diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/stream_encoder.h b/drivers/gpu/drm/amd/display/dc/inc/hw/stream_encoder.h +index 8ba73a474014..8aafed8793df 100644 +--- a/drivers/gpu/drm/amd/display/dc/inc/hw/stream_encoder.h ++++ b/drivers/gpu/drm/amd/display/dc/inc/hw/stream_encoder.h +@@ -67,8 +67,7 @@ struct encoder_info_frame { + + struct encoder_unblank_param { + struct dc_link_settings link_settings; +- unsigned int pixel_clk_khz; +- enum dc_pixel_encoding pixel_encoding; ++ struct dc_crtc_timing timing; + }; + + struct encoder_set_dp_phy_pattern_param { +-- +2.17.1 + |