diff options
Diffstat (limited to 'common/recipes-kernel/linux/linux-yocto-4.19.8/1636-drm-amd-display-Fix-setting-DP_VID_N_MUL.patch')
| -rw-r--r-- | common/recipes-kernel/linux/linux-yocto-4.19.8/1636-drm-amd-display-Fix-setting-DP_VID_N_MUL.patch | 90 |
1 files changed, 90 insertions, 0 deletions
diff --git a/common/recipes-kernel/linux/linux-yocto-4.19.8/1636-drm-amd-display-Fix-setting-DP_VID_N_MUL.patch b/common/recipes-kernel/linux/linux-yocto-4.19.8/1636-drm-amd-display-Fix-setting-DP_VID_N_MUL.patch new file mode 100644 index 00000000..5f639690 --- /dev/null +++ b/common/recipes-kernel/linux/linux-yocto-4.19.8/1636-drm-amd-display-Fix-setting-DP_VID_N_MUL.patch @@ -0,0 +1,90 @@ +From 0bf19a35988602d719e6f4eb1828fde251943871 Mon Sep 17 00:00:00 2001 +From: Eric Bernstein <eric.bernstein@amd.com> +Date: Fri, 17 Aug 2018 17:57:44 -0400 +Subject: [PATCH 1636/2940] drm/amd/display: Fix setting DP_VID_N_MUL + +[Why] +Need to set VID_N_MUL for 4:2:0 cases + +[How] +Move setting to enc1_stream_encoder_dp_unblank and +ensure it is also set for non-4:2:0 cases. + +Change-Id: If17faba806244d6800ec9ec64990684675f82d0f +Signed-off-by: Eric Bernstein <eric.bernstein@amd.com> +--- + .../drm/amd/display/dc/dce110/dce110_hw_sequencer.c | 1 + + .../drm/amd/display/dc/dcn10/dcn10_stream_encoder.c | 13 +++++++++---- + .../gpu/drm/amd/display/dc/inc/hw/stream_encoder.h | 1 + + 3 files changed, 11 insertions(+), 4 deletions(-) + +diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c +index f42721482d8c..cc85a82e4417 100644 +--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c ++++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c +@@ -1054,6 +1054,7 @@ void dce110_unblank_stream(struct pipe_ctx *pipe_ctx, + /* only 3 items below are used by unblank */ + params.pixel_clk_khz = pipe_ctx->stream->timing.pix_clk_100hz / 10; + params.link_settings.link_rate = link_settings->link_rate; ++ params.pixel_encoding = pipe_ctx->stream->timing.pixel_encoding; + + if (dc_is_dp_signal(pipe_ctx->stream->signal)) + pipe_ctx->stream_res.stream_enc->funcs->dp_unblank(pipe_ctx->stream_res.stream_enc, ¶ms); +diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c +index d370152018f8..d2a15d2e9561 100644 +--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c ++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c +@@ -298,7 +298,6 @@ void enc1_stream_encoder_dp_set_stream_attribute( + break; + case PIXEL_ENCODING_YCBCR420: + dp_pixel_encoding = DP_PIXEL_ENCODING_TYPE_YCBCR420; +- REG_UPDATE(DP_VID_TIMING, DP_VID_N_MUL, 1); + break; + default: + dp_pixel_encoding = DP_PIXEL_ENCODING_TYPE_RGB444; +@@ -833,13 +832,17 @@ void enc1_stream_encoder_dp_unblank( + if (param->link_settings.link_rate != LINK_RATE_UNKNOWN) { + uint32_t n_vid = 0x8000; + uint32_t m_vid; ++ uint32_t n_multiply = 0; ++ uint64_t m_vid_l = n_vid; ++ ++ /* YCbCr 4:2:0 : Computed VID_M will be 2X the input rate */ ++ if (param->pixel_encoding == PIXEL_ENCODING_YCBCR420) ++ n_multiply = 1; + + /* M / N = Fstream / Flink + * m_vid / n_vid = pixel rate / link rate + */ + +- uint64_t m_vid_l = n_vid; +- + m_vid_l *= param->pixel_clk_khz; + m_vid_l = div_u64(m_vid_l, + param->link_settings.link_rate +@@ -859,7 +862,9 @@ void enc1_stream_encoder_dp_unblank( + + REG_UPDATE(DP_VID_M, DP_VID_M, m_vid); + +- REG_UPDATE(DP_VID_TIMING, DP_VID_M_N_GEN_EN, 1); ++ REG_UPDATE_2(DP_VID_TIMING, ++ DP_VID_M_N_GEN_EN, 1, ++ DP_VID_N_MUL, n_multiply); + } + + /* set DIG_START to 0x1 to resync FIFO */ +diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/stream_encoder.h b/drivers/gpu/drm/amd/display/dc/inc/hw/stream_encoder.h +index 4051493557bc..8ba73a474014 100644 +--- a/drivers/gpu/drm/amd/display/dc/inc/hw/stream_encoder.h ++++ b/drivers/gpu/drm/amd/display/dc/inc/hw/stream_encoder.h +@@ -68,6 +68,7 @@ struct encoder_info_frame { + struct encoder_unblank_param { + struct dc_link_settings link_settings; + unsigned int pixel_clk_khz; ++ enum dc_pixel_encoding pixel_encoding; + }; + + struct encoder_set_dp_phy_pattern_param { +-- +2.17.1 + |