diff options
Diffstat (limited to 'common/recipes-kernel/linux/linux-yocto-4.19.8/1632-drm-amdgpu-enable-gfxoff-again-on-raven-series-v2.patch')
| -rw-r--r-- | common/recipes-kernel/linux/linux-yocto-4.19.8/1632-drm-amdgpu-enable-gfxoff-again-on-raven-series-v2.patch | 148 |
1 files changed, 148 insertions, 0 deletions
diff --git a/common/recipes-kernel/linux/linux-yocto-4.19.8/1632-drm-amdgpu-enable-gfxoff-again-on-raven-series-v2.patch b/common/recipes-kernel/linux/linux-yocto-4.19.8/1632-drm-amdgpu-enable-gfxoff-again-on-raven-series-v2.patch new file mode 100644 index 00000000..db2881f4 --- /dev/null +++ b/common/recipes-kernel/linux/linux-yocto-4.19.8/1632-drm-amdgpu-enable-gfxoff-again-on-raven-series-v2.patch @@ -0,0 +1,148 @@ +From 1c1aa6a7a79cde0afe3667d5eca7570fd18bca3e Mon Sep 17 00:00:00 2001 +From: Huang Rui <ray.huang@amd.com> +Date: Wed, 13 Mar 2019 20:21:00 +0800 +Subject: [PATCH 1632/2940] drm/amdgpu: enable gfxoff again on raven series + (v2) + +This patch enables gfxoff and stutter mode again, since we take more testing on +raven series. For raven2 and picasso, we can enable it directly. And for raven, +we need check the RLC/SMC ucode version cannot be less than #531/0x1e45. + +v2: add smc version checking for raven. + +Signed-off-by: Huang Rui <ray.huang@amd.com> +Reviewed-by: Alex Deucher <alexander.deucher@amd.com> (v1) +Tested-by: Likun Gao <Likun.Gao@amd.com> (v2) +--- + drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 2 ++ + drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 4 ++-- + drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 21 +++++++++++++++++++ + .../gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c | 13 ++++-------- + .../drm/amd/powerplay/smumgr/smu10_smumgr.c | 4 ++++ + 5 files changed, 33 insertions(+), 11 deletions(-) + +diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +index ff6c00085616..5062554817fb 100644 +--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c ++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +@@ -1556,6 +1556,8 @@ static int amdgpu_device_ip_early_init(struct amdgpu_device *adev) + } + + adev->pm.pp_feature = amdgpu_pp_feature_mask; ++ if (amdgpu_sriov_vf(adev)) ++ adev->pm.pp_feature &= ~PP_GFXOFF_MASK; + + for (i = 0; i < adev->num_ip_blocks; i++) { + if ((amdgpu_ip_block_mask & (1 << i)) == 0) { +diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c +index 5d686e4aa4ae..2d1e9d9d70dc 100644 +--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c ++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c +@@ -123,8 +123,8 @@ uint amdgpu_pg_mask = 0xffffffff; + uint amdgpu_sdma_phase_quantum = 32; + char *amdgpu_disable_cu = NULL; + char *amdgpu_virtual_display = NULL; +-/* OverDrive(bit 14),gfxoff(bit 15),stutter mode(bit 17) disabled by default*/ +-uint amdgpu_pp_feature_mask = 0xfffd3fff; ++/* OverDrive(bit 14) disabled by default*/ ++uint amdgpu_pp_feature_mask = 0xffffbfff; + int amdgpu_ngg = 0; + int amdgpu_prim_buf_per_se = 0; + int amdgpu_pos_buf_per_se = 0; +diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c +index d207e401322c..db5f9e46862a 100644 +--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c ++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c +@@ -578,6 +578,26 @@ static void gfx_v9_0_check_fw_write_wait(struct amdgpu_device *adev) + } + } + ++static void gfx_v9_0_check_if_need_gfxoff(struct amdgpu_device *adev) ++{ ++ switch (adev->asic_type) { ++ case CHIP_VEGA10: ++ case CHIP_VEGA12: ++ case CHIP_VEGA20: ++ break; ++ case CHIP_RAVEN: ++ if (adev->rev_id >= 0x8 || adev->pdev->device == 0x15d8) ++ break; ++ if ((adev->gfx.rlc_fw_version < 531) || ++ (adev->gfx.rlc_feature_version < 1) || ++ !adev->gfx.rlc.is_rlc_v2_1) ++ adev->pm.pp_feature &= ~PP_GFXOFF_MASK; ++ break; ++ default: ++ break; ++ } ++} ++ + static int gfx_v9_0_init_microcode(struct amdgpu_device *adev) + { + const char *chip_name; +@@ -830,6 +850,7 @@ static int gfx_v9_0_init_microcode(struct amdgpu_device *adev) + } + + out: ++ gfx_v9_0_check_if_need_gfxoff(adev); + gfx_v9_0_check_fw_write_wait(adev); + if (err) { + dev_err(adev->dev, +diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c +index 0ad8fe4a6277..f32e3d0aaea6 100644 +--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c ++++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c +@@ -114,11 +114,6 @@ static int smu10_initialize_dpm_defaults(struct pp_hwmgr *hwmgr) + smu10_data->num_active_display = 0; + smu10_data->deep_sleep_dcefclk = 0; + +- if (hwmgr->feature_mask & PP_GFXOFF_MASK) +- smu10_data->gfx_off_controled_by_driver = true; +- else +- smu10_data->gfx_off_controled_by_driver = false; +- + phm_cap_unset(hwmgr->platform_descriptor.platformCaps, + PHM_PlatformCaps_SclkDeepSleep); + +@@ -330,9 +325,9 @@ static bool smu10_is_gfx_on(struct pp_hwmgr *hwmgr) + + static int smu10_disable_gfx_off(struct pp_hwmgr *hwmgr) + { +- struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend); ++ struct amdgpu_device *adev = hwmgr->adev; + +- if (smu10_data->gfx_off_controled_by_driver) { ++ if (adev->pm.pp_feature & PP_GFXOFF_MASK) { + smum_send_msg_to_smc(hwmgr, PPSMC_MSG_DisableGfxOff); + + /* confirm gfx is back to "on" state */ +@@ -350,9 +345,9 @@ static int smu10_disable_dpm_tasks(struct pp_hwmgr *hwmgr) + + static int smu10_enable_gfx_off(struct pp_hwmgr *hwmgr) + { +- struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend); ++ struct amdgpu_device *adev = hwmgr->adev; + +- if (smu10_data->gfx_off_controled_by_driver) ++ if (adev->pm.pp_feature & PP_GFXOFF_MASK) + smum_send_msg_to_smc(hwmgr, PPSMC_MSG_EnableGfxOff); + + return 0; +diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/smu10_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/smu10_smumgr.c +index d111dd4e03d7..6d11076a79ba 100644 +--- a/drivers/gpu/drm/amd/powerplay/smumgr/smu10_smumgr.c ++++ b/drivers/gpu/drm/amd/powerplay/smumgr/smu10_smumgr.c +@@ -212,6 +212,10 @@ static int smu10_start_smu(struct pp_hwmgr *hwmgr) + hwmgr->smu_version = smu10_read_arg_from_smc(hwmgr); + adev->pm.fw_version = hwmgr->smu_version >> 8; + ++ if (adev->rev_id < 0x8 && adev->pdev->device != 0x15d8 && ++ adev->pm.fw_version < 0x1e45) ++ adev->pm.pp_feature &= ~PP_GFXOFF_MASK; ++ + if (smu10_verify_smc_interface(hwmgr)) + return -EINVAL; + +-- +2.17.1 + |