diff options
Diffstat (limited to 'common/recipes-kernel/linux/linux-yocto-4.19.8/1574-drm-amd-powerplay-correct-power-reading-on-fiji.patch')
| -rw-r--r-- | common/recipes-kernel/linux/linux-yocto-4.19.8/1574-drm-amd-powerplay-correct-power-reading-on-fiji.patch | 41 |
1 files changed, 41 insertions, 0 deletions
diff --git a/common/recipes-kernel/linux/linux-yocto-4.19.8/1574-drm-amd-powerplay-correct-power-reading-on-fiji.patch b/common/recipes-kernel/linux/linux-yocto-4.19.8/1574-drm-amd-powerplay-correct-power-reading-on-fiji.patch new file mode 100644 index 00000000..9cd9caae --- /dev/null +++ b/common/recipes-kernel/linux/linux-yocto-4.19.8/1574-drm-amd-powerplay-correct-power-reading-on-fiji.patch @@ -0,0 +1,41 @@ +From 167bf1b482947d1f9ddefd2af713ece10a8ae332 Mon Sep 17 00:00:00 2001 +From: Evan Quan <evan.quan@amd.com> +Date: Mon, 25 Feb 2019 16:44:36 +0800 +Subject: [PATCH 1574/2940] drm/amd/powerplay: correct power reading on fiji + +Set sampling period as 500ms to provide a smooth power +reading output. Also, correct the register for power +reading. + +Change-Id: I13935f3e7fcd026d34aa6a68cf7f683dc6785ab7 +Signed-off-by: Evan Quan <evan.quan@amd.com> +Reviewed-by: Feifei Xu <Feifei.Xu@amd.com> +--- + drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c | 6 +++--- + 1 file changed, 3 insertions(+), 3 deletions(-) + +diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c +index 48187acac59e..83d3d935f3ac 100644 +--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c ++++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c +@@ -3491,14 +3491,14 @@ static int smu7_get_gpu_power(struct pp_hwmgr *hwmgr, u32 *query) + + smum_send_msg_to_smc(hwmgr, PPSMC_MSG_PmStatusLogStart); + cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, +- ixSMU_PM_STATUS_94, 0); ++ ixSMU_PM_STATUS_95, 0); + + for (i = 0; i < 10; i++) { +- mdelay(1); ++ mdelay(500); + smum_send_msg_to_smc(hwmgr, PPSMC_MSG_PmStatusLogSample); + tmp = cgs_read_ind_register(hwmgr->device, + CGS_IND_REG__SMC, +- ixSMU_PM_STATUS_94); ++ ixSMU_PM_STATUS_95); + if (tmp != 0) + break; + } +-- +2.17.1 + |