diff options
Diffstat (limited to 'common/recipes-kernel/linux/linux-yocto-4.19.8/1565-drm-amd-amdgpu-Add-ENGINE_CNTL-register-to-vcn10-hea.patch')
| -rw-r--r-- | common/recipes-kernel/linux/linux-yocto-4.19.8/1565-drm-amd-amdgpu-Add-ENGINE_CNTL-register-to-vcn10-hea.patch | 49 |
1 files changed, 49 insertions, 0 deletions
diff --git a/common/recipes-kernel/linux/linux-yocto-4.19.8/1565-drm-amd-amdgpu-Add-ENGINE_CNTL-register-to-vcn10-hea.patch b/common/recipes-kernel/linux/linux-yocto-4.19.8/1565-drm-amd-amdgpu-Add-ENGINE_CNTL-register-to-vcn10-hea.patch new file mode 100644 index 00000000..ecd1e9f0 --- /dev/null +++ b/common/recipes-kernel/linux/linux-yocto-4.19.8/1565-drm-amd-amdgpu-Add-ENGINE_CNTL-register-to-vcn10-hea.patch @@ -0,0 +1,49 @@ +From 3ecbc48f94bdfbf0666f39bb285189db7777d6be Mon Sep 17 00:00:00 2001 +From: Tom St Denis <tom.stdenis@amd.com> +Date: Mon, 4 Mar 2019 10:58:44 -0500 +Subject: [PATCH 1565/2940] drm/amd/amdgpu: Add ENGINE_CNTL register to vcn10 + headers +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Signed-off-by: Tom St Denis <tom.stdenis@amd.com> +Acked-by: Christian König <christian.koenig@amd.com> +Reviewed-by: Alex Deucher <alexander.deucher@amd.com> +--- + drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_offset.h | 2 ++ + drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h | 5 +++++ + 2 files changed, 7 insertions(+) + +diff --git a/drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_offset.h +index 442ca7c471a5..6109f5ad25ad 100644 +--- a/drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_offset.h ++++ b/drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_offset.h +@@ -141,6 +141,8 @@ + #define mmUVD_GPCOM_VCPU_DATA0_BASE_IDX 1 + #define mmUVD_GPCOM_VCPU_DATA1 0x03c5 + #define mmUVD_GPCOM_VCPU_DATA1_BASE_IDX 1 ++#define mmUVD_ENGINE_CNTL 0x03c6 ++#define mmUVD_ENGINE_CNTL_BASE_IDX 1 + #define mmUVD_UDEC_DBW_UV_ADDR_CONFIG 0x03d2 + #define mmUVD_UDEC_DBW_UV_ADDR_CONFIG_BASE_IDX 1 + #define mmUVD_UDEC_ADDR_CONFIG 0x03d3 +diff --git a/drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h +index 63457f9df4c5..f84bed6eecb9 100644 +--- a/drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h ++++ b/drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h +@@ -312,6 +312,11 @@ + //UVD_GPCOM_VCPU_DATA1 + #define UVD_GPCOM_VCPU_DATA1__DATA1__SHIFT 0x0 + #define UVD_GPCOM_VCPU_DATA1__DATA1_MASK 0xFFFFFFFFL ++//UVD_ENGINE_CNTL ++#define UVD_ENGINE_CNTL__ENGINE_START_MASK 0x1 ++#define UVD_ENGINE_CNTL__ENGINE_START__SHIFT 0x0 ++#define UVD_ENGINE_CNTL__ENGINE_START_MODE_MASK 0x2 ++#define UVD_ENGINE_CNTL__ENGINE_START_MODE__SHIFT 0x1 + //UVD_UDEC_DBW_UV_ADDR_CONFIG + #define UVD_UDEC_DBW_UV_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0 + #define UVD_UDEC_DBW_UV_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x3 +-- +2.17.1 + |