diff options
Diffstat (limited to 'common/recipes-kernel/linux/linux-yocto-4.19.8/1555-drm-amdgpu-also-reroute-VMC-and-UMD-to-IH-ring-1-on-.patch')
| -rw-r--r-- | common/recipes-kernel/linux/linux-yocto-4.19.8/1555-drm-amdgpu-also-reroute-VMC-and-UMD-to-IH-ring-1-on-.patch | 82 |
1 files changed, 82 insertions, 0 deletions
diff --git a/common/recipes-kernel/linux/linux-yocto-4.19.8/1555-drm-amdgpu-also-reroute-VMC-and-UMD-to-IH-ring-1-on-.patch b/common/recipes-kernel/linux/linux-yocto-4.19.8/1555-drm-amdgpu-also-reroute-VMC-and-UMD-to-IH-ring-1-on-.patch new file mode 100644 index 00000000..d2723bc2 --- /dev/null +++ b/common/recipes-kernel/linux/linux-yocto-4.19.8/1555-drm-amdgpu-also-reroute-VMC-and-UMD-to-IH-ring-1-on-.patch @@ -0,0 +1,82 @@ +From e8afa813328c6a5912528b5f3ebcec421fb63402 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Christian=20K=C3=B6nig?= <christian.koenig@amd.com> +Date: Mon, 4 Mar 2019 19:34:34 +0100 +Subject: [PATCH 1555/2940] drm/amdgpu: also reroute VMC and UMD to IH ring 1 + on Vega 20 +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Same patch we alredy did for Vega10. Just re-route page faults to a separate +ring to avoid drowning in interrupts. + +Signed-off-by: Christian König <christian.koenig@amd.com> +Reviewed-by: Alex Deucher <alexander.deucher@amd.com> +--- + drivers/gpu/drm/amd/amdgpu/psp_v11_0.c | 36 ++++++++++++++++++++++++++ + 1 file changed, 36 insertions(+) + +diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c b/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c +index b84075687f41..bfae24b55c95 100644 +--- a/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c ++++ b/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c +@@ -33,6 +33,9 @@ + #include "sdma0/sdma0_4_0_offset.h" + #include "nbio/nbio_7_4_offset.h" + ++#include "oss/osssys_4_0_offset.h" ++#include "oss/osssys_4_0_sh_mask.h" ++ + MODULE_FIRMWARE("amdgpu/vega20_sos.bin"); + MODULE_FIRMWARE("amdgpu/vega20_asd.bin"); + MODULE_FIRMWARE("amdgpu/vega20_ta.bin"); +@@ -234,6 +237,37 @@ static int psp_v11_0_bootloader_load_sos(struct psp_context *psp) + return ret; + } + ++static void psp_v11_0_reroute_ih(struct psp_context *psp) ++{ ++ struct amdgpu_device *adev = psp->adev; ++ uint32_t tmp; ++ ++ /* Change IH ring for VMC */ ++ tmp = REG_SET_FIELD(0, IH_CLIENT_CFG_DATA, CREDIT_RETURN_ADDR, 0x1244b); ++ tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, CLIENT_TYPE, 1); ++ tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, RING_ID, 1); ++ ++ WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, 3); ++ WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, tmp); ++ WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, GFX_CTRL_CMD_ID_GBR_IH_SET); ++ ++ mdelay(20); ++ psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64), ++ 0x80000000, 0x8000FFFF, false); ++ ++ /* Change IH ring for UMC */ ++ tmp = REG_SET_FIELD(0, IH_CLIENT_CFG_DATA, CREDIT_RETURN_ADDR, 0x1216b); ++ tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, RING_ID, 1); ++ ++ WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, 4); ++ WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, tmp); ++ WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, GFX_CTRL_CMD_ID_GBR_IH_SET); ++ ++ mdelay(20); ++ psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64), ++ 0x80000000, 0x8000FFFF, false); ++} ++ + static int psp_v11_0_ring_init(struct psp_context *psp, + enum psp_ring_type ring_type) + { +@@ -241,6 +275,8 @@ static int psp_v11_0_ring_init(struct psp_context *psp, + struct psp_ring *ring; + struct amdgpu_device *adev = psp->adev; + ++ psp_v11_0_reroute_ih(psp); ++ + ring = &psp->km_ring; + + ring->ring_type = ring_type; +-- +2.17.1 + |