diff options
Diffstat (limited to 'common/recipes-kernel/linux/linux-yocto-4.19.8/1543-drm-amd-display-Add-pp_smu-null-pointer-check.patch')
| -rw-r--r-- | common/recipes-kernel/linux/linux-yocto-4.19.8/1543-drm-amd-display-Add-pp_smu-null-pointer-check.patch | 91 |
1 files changed, 91 insertions, 0 deletions
diff --git a/common/recipes-kernel/linux/linux-yocto-4.19.8/1543-drm-amd-display-Add-pp_smu-null-pointer-check.patch b/common/recipes-kernel/linux/linux-yocto-4.19.8/1543-drm-amd-display-Add-pp_smu-null-pointer-check.patch new file mode 100644 index 00000000..ce64a227 --- /dev/null +++ b/common/recipes-kernel/linux/linux-yocto-4.19.8/1543-drm-amd-display-Add-pp_smu-null-pointer-check.patch @@ -0,0 +1,91 @@ +From b8d39ebc1ab597322a13100bad1050bbba8f9ff8 Mon Sep 17 00:00:00 2001 +From: Charlene Liu <charlene.liu@amd.com> +Date: Tue, 19 Feb 2019 12:14:19 -0500 +Subject: [PATCH 1543/2940] drm/amd/display: Add pp_smu null pointer check + +res_pool->pp_smu may be NULL. Check before use + +Change-Id: Ib038334b2374b10012fc374a3aeb5c417655c7c9 +Signed-off-by: Charlene Liu <charlene.liu@amd.com> +Reviewed-by: Krunoslav Kovac <Krunoslav.Kovac@amd.com> +Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> +Signed-off-by: Chaudhary Amit Kumar <Chaudharyamit.Kumar@amd.com> +--- + drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c | 6 ++++-- + drivers/gpu/drm/amd/display/dc/dcn10/dcn10_clk_mgr.c | 11 ++++++----- + 2 files changed, 10 insertions(+), 7 deletions(-) + +diff --git a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c +index 2a807b9f77f7..8ee182be394a 100644 +--- a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c ++++ b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c +@@ -1391,12 +1391,14 @@ void dcn_bw_update_from_pplib(struct dc *dc) + + void dcn_bw_notify_pplib_of_wm_ranges(struct dc *dc) + { +- struct pp_smu_funcs_rv *pp = &dc->res_pool->pp_smu->rv_funcs; ++ struct pp_smu_funcs_rv *pp = NULL; + struct pp_smu_wm_range_sets ranges = {0}; + int min_fclk_khz, min_dcfclk_khz, socclk_khz; + const int overdrive = 5000000; /* 5 GHz to cover Overdrive */ + +- if (!pp->set_wm_ranges) ++ if (dc->res_pool->pp_smu) ++ pp = &dc->res_pool->pp_smu->rv_funcs; ++ if (!pp || !pp->set_wm_ranges) + return; + + kernel_fpu_begin(); +diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_clk_mgr.c +index f8a912fb3680..a567d44d4978 100644 +--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_clk_mgr.c ++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_clk_mgr.c +@@ -171,7 +171,7 @@ static void dcn1_update_clocks(struct clk_mgr *clk_mgr, + struct pp_smu_display_requirement_rv *smu_req_cur = + &dc->res_pool->pp_smu_req; + struct pp_smu_display_requirement_rv smu_req = *smu_req_cur; +- struct pp_smu_funcs_rv *pp_smu = &dc->res_pool->pp_smu->rv_funcs; ++ struct pp_smu_funcs_rv *pp_smu = NULL; + bool send_request_to_increase = false; + bool send_request_to_lower = false; + int display_count; +@@ -179,7 +179,8 @@ static void dcn1_update_clocks(struct clk_mgr *clk_mgr, + bool enter_display_off = false; + + display_count = get_active_display_cnt(dc, context); +- ++ if (dc->res_pool->pp_smu) ++ pp_smu = &dc->res_pool->pp_smu->rv_funcs; + if (display_count == 0) + enter_display_off = true; + +@@ -189,7 +190,7 @@ static void dcn1_update_clocks(struct clk_mgr *clk_mgr, + * if function pointer not set up, this message is + * sent as part of pplib_apply_display_requirements. + */ +- if (pp_smu->set_display_count) ++ if (pp_smu && pp_smu->set_display_count) + pp_smu->set_display_count(&pp_smu->pp_smu, display_count); + + smu_req.display_count = display_count; +@@ -239,7 +240,7 @@ static void dcn1_update_clocks(struct clk_mgr *clk_mgr, + */ + if (send_request_to_increase) { + /*use dcfclk to request voltage*/ +- if (pp_smu->set_hard_min_fclk_by_freq && ++ if (pp_smu && pp_smu->set_hard_min_fclk_by_freq && + pp_smu->set_hard_min_dcfclk_by_freq && + pp_smu->set_min_deep_sleep_dcfclk) { + +@@ -261,7 +262,7 @@ static void dcn1_update_clocks(struct clk_mgr *clk_mgr, + + if (!send_request_to_increase && send_request_to_lower) { + /*use dcfclk to request voltage*/ +- if (pp_smu->set_hard_min_fclk_by_freq && ++ if (pp_smu && pp_smu->set_hard_min_fclk_by_freq && + pp_smu->set_hard_min_dcfclk_by_freq && + pp_smu->set_min_deep_sleep_dcfclk) { + +-- +2.17.1 + |