diff options
Diffstat (limited to 'common/recipes-kernel/linux/linux-yocto-4.19.8/1532-drm-amd-display-Drop-underlay-plane-support.patch')
| -rw-r--r-- | common/recipes-kernel/linux/linux-yocto-4.19.8/1532-drm-amd-display-Drop-underlay-plane-support.patch | 236 |
1 files changed, 236 insertions, 0 deletions
diff --git a/common/recipes-kernel/linux/linux-yocto-4.19.8/1532-drm-amd-display-Drop-underlay-plane-support.patch b/common/recipes-kernel/linux/linux-yocto-4.19.8/1532-drm-amd-display-Drop-underlay-plane-support.patch new file mode 100644 index 00000000..04e83e8b --- /dev/null +++ b/common/recipes-kernel/linux/linux-yocto-4.19.8/1532-drm-amd-display-Drop-underlay-plane-support.patch @@ -0,0 +1,236 @@ +From 7dccdebc334dcd664dcd0a17bbd27f7e613b2fc4 Mon Sep 17 00:00:00 2001 +From: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> +Date: Fri, 18 Jan 2019 13:42:34 -0500 +Subject: [PATCH 1532/2940] drm/amd/display: Drop underlay plane support + +[Why] +Primary and underlay planes were previously exposed to DRM by using +max_planes and max_slave_planes. + +The value for max_planes was always pipe_count + has_underlay. +If there was an underlay pipe, then max_slave_planes = 1. + +Raven has pipe_count = 4, max_planes = 4, and max_slave_planes = 1. +So during plane initialziation it was actually "creating" +1 overlay plane and 3 primary planes... or it would be, had its +plane_type array not been dm_plane_type_default, which will only create +DRM_PLANE_TYPE_PRIMARY planes. + +We can expose primary planes as supporting more than one CRTC at a time +to more closely resemble plane behavior on DCN but userspace doesn't +really expect planes to be used in this manner and will either +ignore the planes or crash. + +Planes with index greater than max_streams are marked as supporting +all CRTCs. No ASIC currently has primary plane count greater than the +stream count but we shouldn't expose more than necessary. + +[How] +Drop support for underlay planes. They aren't well tested and don't +fully work right at the moment. + +Only create one primary plane per CRTC so we're not creating overlays. + +Initialize plane types directly instead of referencing a misleading +array of plane types. + +Change-Id: Ibdf1caa8a2be42df6f7574dae97c49734fa44151 +Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> +Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> +Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> +Signed-off-by: Chaudhary Amit Kumar <Chaudharyamit.Kumar@amd.com> +--- + .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 78 ++++++------------- + 1 file changed, 22 insertions(+), 56 deletions(-) + +diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +index 05f44e33edea..e88a75a870f4 100644 +--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c ++++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +@@ -138,28 +138,6 @@ static void prepare_flip_isr(struct amdgpu_crtc *acrtc); + static void handle_cursor_update(struct drm_plane *plane, + struct drm_plane_state *old_plane_state); + +-static const enum drm_plane_type dm_plane_type_default[AMDGPU_MAX_PLANES] = { +- DRM_PLANE_TYPE_PRIMARY, +- DRM_PLANE_TYPE_PRIMARY, +- DRM_PLANE_TYPE_PRIMARY, +- DRM_PLANE_TYPE_PRIMARY, +- DRM_PLANE_TYPE_PRIMARY, +- DRM_PLANE_TYPE_PRIMARY, +-}; +- +-static const enum drm_plane_type dm_plane_type_carizzo[AMDGPU_MAX_PLANES] = { +- DRM_PLANE_TYPE_PRIMARY, +- DRM_PLANE_TYPE_PRIMARY, +- DRM_PLANE_TYPE_PRIMARY, +- DRM_PLANE_TYPE_OVERLAY,/* YUV Capable Underlay */ +-}; +- +-static const enum drm_plane_type dm_plane_type_stoney[AMDGPU_MAX_PLANES] = { +- DRM_PLANE_TYPE_PRIMARY, +- DRM_PLANE_TYPE_PRIMARY, +- DRM_PLANE_TYPE_OVERLAY, /* YUV Capable Underlay */ +-}; +- + /* + * dm_vblank_get_counter + * +@@ -1843,8 +1821,8 @@ amdgpu_dm_register_backlight_device(struct amdgpu_display_manager *dm) + #endif + + static int initialize_plane(struct amdgpu_display_manager *dm, +- struct amdgpu_mode_info *mode_info, +- int plane_id) ++ struct amdgpu_mode_info *mode_info, int plane_id, ++ enum drm_plane_type plane_type) + { + struct drm_plane *plane; + unsigned long possible_crtcs; +@@ -1857,15 +1835,16 @@ static int initialize_plane(struct amdgpu_display_manager *dm, + DRM_ERROR("KMS: Failed to allocate plane\n"); + return -ENOMEM; + } +- plane->type = mode_info->plane_type[plane_id]; ++ plane->type = plane_type; + +- /* +- * HACK: IGT tests expect that each plane can only have +- * one possible CRTC. For now, set one CRTC for each +- * plane that is not an underlay, but still allow multiple +- * CRTCs for underlay planes. +- */ + possible_crtcs = 1 << plane_id; ++ ++ /* ++ * HACK: IGT tests expect that the primary plane for a CRTC ++ * can only have one possible CRTC. Only expose support for ++ * any CRTC if they're not going to be used as a primary plane ++ * for a CRTC - like overlay or underlay planes. ++ */ + if (plane_id >= dm->dc->caps.max_streams) + possible_crtcs = 0xff; + +@@ -1918,7 +1897,7 @@ static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev) + struct amdgpu_encoder *aencoder = NULL; + struct amdgpu_mode_info *mode_info = &adev->mode_info; + uint32_t link_cnt; +- int32_t total_overlay_planes, total_primary_planes; ++ int32_t primary_planes; + enum dc_connection_type new_connection_type = dc_connection_none; + + link_cnt = dm->dc->caps.max_links; +@@ -1927,21 +1906,18 @@ static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev) + return -EINVAL; + } + +- /* Identify the number of planes to be initialized */ +- total_overlay_planes = dm->dc->caps.max_slave_planes; +- total_primary_planes = dm->dc->caps.max_planes - dm->dc->caps.max_slave_planes; ++ /* There is one primary plane per CRTC */ ++ primary_planes = dm->dc->caps.max_streams; ++ ASSERT(primary_planes < AMDGPU_MAX_PLANES); + +- /* First initialize overlay planes, index starting after primary planes */ +- for (i = (total_overlay_planes - 1); i >= 0; i--) { +- if (initialize_plane(dm, mode_info, (total_primary_planes + i))) { +- DRM_ERROR("KMS: Failed to initialize overlay plane\n"); +- goto fail; +- } +- } ++ /* ++ * Initialize primary planes, implicit planes for legacy IOCTLS. ++ * Order is reversed to match iteration order in atomic check. ++ */ ++ for (i = (primary_planes - 1); i >= 0; i--) { ++ if (initialize_plane(dm, mode_info, i, ++ DRM_PLANE_TYPE_PRIMARY)) { + +- /* Initialize primary planes */ +- for (i = (total_primary_planes - 1); i >= 0; i--) { +- if (initialize_plane(dm, mode_info, i)) { + DRM_ERROR("KMS: Failed to initialize primary plane\n"); + goto fail; + } +@@ -2045,7 +2021,7 @@ static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev) + fail: + kfree(aencoder); + kfree(aconnector); +- for (i = 0; i < dm->dc->caps.max_planes; i++) ++ for (i = 0; i < primary_planes; i++) + kfree(mode_info->planes[i]); + return -EINVAL; + } +@@ -2212,53 +2188,45 @@ static int dm_early_init(void *handle) + adev->mode_info.num_crtc = 6; + adev->mode_info.num_hpd = 6; + adev->mode_info.num_dig = 6; +- adev->mode_info.plane_type = dm_plane_type_default; + break; + case CHIP_KAVERI: + adev->mode_info.num_crtc = 4; + adev->mode_info.num_hpd = 6; + adev->mode_info.num_dig = 7; +- adev->mode_info.plane_type = dm_plane_type_default; + break; + case CHIP_KABINI: + case CHIP_MULLINS: + adev->mode_info.num_crtc = 2; + adev->mode_info.num_hpd = 6; + adev->mode_info.num_dig = 6; +- adev->mode_info.plane_type = dm_plane_type_default; + break; + case CHIP_FIJI: + case CHIP_TONGA: + adev->mode_info.num_crtc = 6; + adev->mode_info.num_hpd = 6; + adev->mode_info.num_dig = 7; +- adev->mode_info.plane_type = dm_plane_type_default; + break; + case CHIP_CARRIZO: + adev->mode_info.num_crtc = 3; + adev->mode_info.num_hpd = 6; + adev->mode_info.num_dig = 9; +- adev->mode_info.plane_type = dm_plane_type_carizzo; + break; + case CHIP_STONEY: + adev->mode_info.num_crtc = 2; + adev->mode_info.num_hpd = 6; + adev->mode_info.num_dig = 9; +- adev->mode_info.plane_type = dm_plane_type_stoney; + break; + case CHIP_POLARIS11: + case CHIP_POLARIS12: + adev->mode_info.num_crtc = 5; + adev->mode_info.num_hpd = 5; + adev->mode_info.num_dig = 5; +- adev->mode_info.plane_type = dm_plane_type_default; + break; + case CHIP_POLARIS10: + case CHIP_VEGAM: + adev->mode_info.num_crtc = 6; + adev->mode_info.num_hpd = 6; + adev->mode_info.num_dig = 6; +- adev->mode_info.plane_type = dm_plane_type_default; + break; + case CHIP_VEGA10: + case CHIP_VEGA12: +@@ -2266,7 +2234,6 @@ static int dm_early_init(void *handle) + adev->mode_info.num_crtc = 6; + adev->mode_info.num_hpd = 6; + adev->mode_info.num_dig = 6; +- adev->mode_info.plane_type = dm_plane_type_default; + break; + #ifdef CONFIG_X86 + case CHIP_RAVEN: +@@ -2274,7 +2241,6 @@ static int dm_early_init(void *handle) + adev->mode_info.num_crtc = 4; + adev->mode_info.num_hpd = 4; + adev->mode_info.num_dig = 4; +- adev->mode_info.plane_type = dm_plane_type_default; + break; + #endif + default: +-- +2.17.1 + |