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Diffstat (limited to 'common/recipes-kernel/linux/linux-yocto-4.19.8/1531-drm-amd-display-Add-plane-capabilities-to-dc_caps.patch')
-rw-r--r--common/recipes-kernel/linux/linux-yocto-4.19.8/1531-drm-amd-display-Add-plane-capabilities-to-dc_caps.patch293
1 files changed, 293 insertions, 0 deletions
diff --git a/common/recipes-kernel/linux/linux-yocto-4.19.8/1531-drm-amd-display-Add-plane-capabilities-to-dc_caps.patch b/common/recipes-kernel/linux/linux-yocto-4.19.8/1531-drm-amd-display-Add-plane-capabilities-to-dc_caps.patch
new file mode 100644
index 00000000..e81ae9b1
--- /dev/null
+++ b/common/recipes-kernel/linux/linux-yocto-4.19.8/1531-drm-amd-display-Add-plane-capabilities-to-dc_caps.patch
@@ -0,0 +1,293 @@
+From edae72d9f7ebd3e0cd0bf697bb86a1f0d007dfa7 Mon Sep 17 00:00:00 2001
+From: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
+Date: Tue, 5 Feb 2019 12:50:01 -0500
+Subject: [PATCH 1531/2940] drm/amd/display: Add plane capabilities to dc_caps
+
+[Why]
+The current dc_caps doesn't provide the information needed to
+determine the count and type of each plane to be exposed to userspace.
+
+There are three types of DRM planes that are exposed to userspace:
+
+1. Primary planes (can be used for modesetting)
+2. Overlay planes (can be blended below or above a primary plane)
+3. Cursor planes (blended topmost)
+
+We need to know the number and type of each in amdgpu_dm to expose
+to userspace.
+
+Hardware supports blending planes below, above or both ways depending
+on the ASIC. Alpha support is also ASIC dependent. Some hardware has
+dedicated pipes for overlays and other hardware combines the pipes.
+
+All of this should be exposed in a way that DM can query and use.
+
+[How]
+Introduce the dc_plane_cap structure that describes the capabilities
+for the hw planes.
+
+It describes:
+- the type of the plane
+- whether the plane can blend with planes below it
+- whether the plane can blend with planes above it
+- whether the plane supports per pixel alpha blending
+- supported formats on the plane (partial list for now)
+
+Pre DCN ASICs don't have their full capabilities described for now.
+They can be updated as needed in the future.
+
+Change-Id: I8d0ab9c7332aff8a3976db852afd1f977ee70e9b
+Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
+Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
+Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/dc.h | 18 +++++++++++++++++
+ .../amd/display/dc/dce100/dce100_resource.c | 8 ++++++++
+ .../amd/display/dc/dce110/dce110_resource.c | 20 +++++++++++++++++++
+ .../amd/display/dc/dce112/dce112_resource.c | 8 ++++++++
+ .../amd/display/dc/dce120/dce120_resource.c | 8 ++++++++
+ .../drm/amd/display/dc/dce80/dce80_resource.c | 17 ++++++++++++++++
+ .../drm/amd/display/dc/dcn10/dcn10_resource.c | 12 +++++++++++
+ 7 files changed, 91 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
+index 6845960fb098..15b7e1d8053e 100644
+--- a/drivers/gpu/drm/amd/display/dc/dc.h
++++ b/drivers/gpu/drm/amd/display/dc/dc.h
+@@ -45,6 +45,7 @@
+ #define DC_VER "3.2.19"
+
+ #define MAX_SURFACES 3
++#define MAX_PLANES 6
+ #define MAX_STREAMS 6
+ #define MAX_SINKS_PER_LINK 4
+
+@@ -56,6 +57,22 @@ struct dc_versions {
+ struct dmcu_version dmcu_version;
+ };
+
++enum dc_plane_type {
++ DC_PLANE_TYPE_INVALID,
++ DC_PLANE_TYPE_DCE_RGB,
++ DC_PLANE_TYPE_DCE_UNDERLAY,
++ DC_PLANE_TYPE_DCN_UNIVERSAL,
++};
++
++struct dc_plane_cap {
++ enum dc_plane_type type;
++ uint32_t blends_with_above : 1;
++ uint32_t blends_with_below : 1;
++ uint32_t per_pixel_alpha : 1;
++ uint32_t supports_argb8888 : 1;
++ uint32_t supports_nv12 : 1;
++};
++
+ struct dc_caps {
+ uint32_t max_streams;
+ uint32_t max_links;
+@@ -76,6 +93,7 @@ struct dc_caps {
+ bool force_dp_tps4_for_cp2520;
+ bool disable_dp_clk_share;
+ bool psp_setup_panel_mode;
++ struct dc_plane_cap planes[MAX_PLANES];
+ };
+
+ struct dc_dcc_surface_param {
+diff --git a/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c b/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c
+index 23044e6723e8..b733dc17db87 100644
+--- a/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c
++++ b/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c
+@@ -378,6 +378,11 @@ static const struct resource_caps res_cap = {
+ .num_ddc = 6,
+ };
+
++static const struct dc_plane_cap plane_cap = {
++ .type = DC_PLANE_TYPE_DCE_RGB,
++ .supports_argb8888 = true,
++};
++
+ #define CTX ctx
+ #define REG(reg) mm ## reg
+
+@@ -1023,6 +1028,9 @@ static bool construct(
+
+ dc->caps.max_planes = pool->base.pipe_count;
+
++ for (i = 0; i < dc->caps.max_planes; ++i)
++ dc->caps.planes[i] = plane_cap;
++
+ if (!resource_construct(num_virtual_links, dc, &pool->base,
+ &res_create_funcs))
+ goto res_create_fail;
+diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c
+index 7549adaa1542..50af7e17db3b 100644
+--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c
++++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c
+@@ -392,6 +392,21 @@ static const struct resource_caps stoney_resource_cap = {
+ .num_ddc = 3,
+ };
+
++static const struct dc_plane_cap plane_cap = {
++ .type = DC_PLANE_TYPE_DCE_RGB,
++ .blends_with_below = true,
++ .blends_with_above = true,
++ .per_pixel_alpha = 1,
++ .supports_argb8888 = true,
++};
++
++static const struct dc_plane_cap underlay_plane_cap = {
++ .type = DC_PLANE_TYPE_DCE_UNDERLAY,
++ .blends_with_above = true,
++ .per_pixel_alpha = 1,
++ .supports_nv12 = true
++};
++
+ #define CTX ctx
+ #define REG(reg) mm ## reg
+
+@@ -1371,6 +1386,11 @@ static bool construct(
+
+ dc->caps.max_planes = pool->base.pipe_count;
+
++ for (i = 0; i < pool->base.underlay_pipe_index; ++i)
++ dc->caps.planes[i] = plane_cap;
++
++ dc->caps.planes[pool->base.underlay_pipe_index] = underlay_plane_cap;
++
+ bw_calcs_init(dc->bw_dceip, dc->bw_vbios, dc->ctx->asic_id);
+
+ bw_calcs_data_update_from_pplib(dc);
+diff --git a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c
+index ea3065d63372..188fc992e941 100644
+--- a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c
++++ b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c
+@@ -397,6 +397,11 @@ static const struct resource_caps polaris_11_resource_cap = {
+ .num_ddc = 5,
+ };
+
++static const struct dc_plane_cap plane_cap = {
++ .type = DC_PLANE_TYPE_DCE_RGB,
++ .supports_argb8888 = true,
++};
++
+ #define CTX ctx
+ #define REG(reg) mm ## reg
+
+@@ -1310,6 +1315,9 @@ static bool construct(
+
+ dc->caps.max_planes = pool->base.pipe_count;
+
++ for (i = 0; i < dc->caps.max_planes; ++i)
++ dc->caps.planes[i] = plane_cap;
++
+ /* Create hardware sequencer */
+ dce112_hw_sequencer_construct(dc);
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c b/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c
+index 312a0aebf91f..01ea503faa12 100644
+--- a/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c
++++ b/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c
+@@ -454,6 +454,11 @@ static const struct resource_caps res_cap = {
+ .num_ddc = 6,
+ };
+
++static const struct dc_plane_cap plane_cap = {
++ .type = DC_PLANE_TYPE_DCE_RGB,
++ .supports_argb8888 = true,
++};
++
+ static const struct dc_debug_options debug_defaults = {
+ .disable_clock_gate = true,
+ };
+@@ -1171,6 +1176,9 @@ static bool construct(
+
+ dc->caps.max_planes = pool->base.pipe_count;
+
++ for (i = 0; i < dc->caps.max_planes; ++i)
++ dc->caps.planes[i] = plane_cap;
++
+ bw_calcs_init(dc->bw_dceip, dc->bw_vbios, dc->ctx->asic_id);
+
+ bw_calcs_data_update_from_pplib(dc);
+diff --git a/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c b/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c
+index c109ace96be9..066fd89747c2 100644
+--- a/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c
++++ b/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c
+@@ -387,6 +387,11 @@ static const struct resource_caps res_cap_83 = {
+ .num_ddc = 2,
+ };
+
++static const struct dc_plane_cap plane_cap = {
++ .type = DC_PLANE_TYPE_DCE_RGB,
++ .supports_argb8888 = true,
++};
++
+ static const struct dce_dmcu_registers dmcu_regs = {
+ DMCU_DCE80_REG_LIST()
+ };
+@@ -1032,6 +1037,10 @@ static bool dce80_construct(
+ }
+
+ dc->caps.max_planes = pool->base.pipe_count;
++
++ for (i = 0; i < dc->caps.max_planes; ++i)
++ dc->caps.planes[i] = plane_cap;
++
+ dc->caps.disable_dp_clk_share = true;
+
+ if (!resource_construct(num_virtual_links, dc, &pool->base,
+@@ -1237,6 +1246,10 @@ static bool dce81_construct(
+ }
+
+ dc->caps.max_planes = pool->base.pipe_count;
++
++ for (i = 0; i < dc->caps.max_planes; ++i)
++ dc->caps.planes[i] = plane_cap;
++
+ dc->caps.disable_dp_clk_share = true;
+
+ if (!resource_construct(num_virtual_links, dc, &pool->base,
+@@ -1438,6 +1451,10 @@ static bool dce83_construct(
+ }
+
+ dc->caps.max_planes = pool->base.pipe_count;
++
++ for (i = 0; i < dc->caps.max_planes; ++i)
++ dc->caps.planes[i] = plane_cap;
++
+ dc->caps.disable_dp_clk_share = true;
+
+ if (!resource_construct(num_virtual_links, dc, &pool->base,
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
+index dd8d189d17c9..9f1a009b19ee 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
+@@ -516,6 +516,15 @@ static const struct resource_caps rv2_res_cap = {
+ };
+ #endif
+
++static const struct dc_plane_cap plane_cap = {
++ .type = DC_PLANE_TYPE_DCN_UNIVERSAL,
++ .blends_with_above = true,
++ .blends_with_below = true,
++ .per_pixel_alpha = true,
++ .supports_argb8888 = true,
++ .supports_nv12 = true
++};
++
+ static const struct dc_debug_options debug_defaults_drv = {
+ .sanity_checks = true,
+ .disable_dmcu = true,
+@@ -1510,6 +1519,9 @@ static bool construct(
+ dcn10_hw_sequencer_construct(dc);
+ dc->caps.max_planes = pool->base.pipe_count;
+
++ for (i = 0; i < dc->caps.max_planes; ++i)
++ dc->caps.planes[i] = plane_cap;
++
+ dc->cap_funcs = cap_funcs;
+
+ return true;
+--
+2.17.1
+
generated by cgit 1.2.3-korg (git 2.39.0) at 2024-04-25 08:12:06 +0000