diff options
Diffstat (limited to 'common/recipes-kernel/linux/linux-yocto-4.19.8/1492-drm-amd-powerplay-add-override-pcie-parameters.patch')
| -rw-r--r-- | common/recipes-kernel/linux/linux-yocto-4.19.8/1492-drm-amd-powerplay-add-override-pcie-parameters.patch | 90 |
1 files changed, 90 insertions, 0 deletions
diff --git a/common/recipes-kernel/linux/linux-yocto-4.19.8/1492-drm-amd-powerplay-add-override-pcie-parameters.patch b/common/recipes-kernel/linux/linux-yocto-4.19.8/1492-drm-amd-powerplay-add-override-pcie-parameters.patch new file mode 100644 index 00000000..3785c9ab --- /dev/null +++ b/common/recipes-kernel/linux/linux-yocto-4.19.8/1492-drm-amd-powerplay-add-override-pcie-parameters.patch @@ -0,0 +1,90 @@ +From e8561a786e152a2f96060b22ced87017d4c3b3d6 Mon Sep 17 00:00:00 2001 +From: Likun Gao <Likun.Gao@amd.com> +Date: Thu, 21 Feb 2019 16:50:23 +0800 +Subject: [PATCH 1492/2940] drm/amd/powerplay: add override pcie parameters + +PCIE parameters should be override to fix the conflict between the ASIC +capabilities and the system capabilities. + +Signed-off-by: Likun Gao <Likun.Gao@amd.com> +Reviewed-by: Gui Chengming <Jack.Gui@amd.com> +Reviewed-by: Huang Rui <ray.huang@amd.com> +Reviewed-by: Alex Deucher <alexander.deucher@amd.com> +--- + drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 46 ++++++++++++++++++++++ + 1 file changed, 46 insertions(+) + +diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c +index f5d6caf11ca3..7857ceb7403f 100644 +--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c ++++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c +@@ -28,6 +28,7 @@ + #include "soc15_common.h" + #include "smu_v11_0.h" + #include "atom.h" ++#include "amd_pcie.h" + + int smu_dpm_set_power_gate(struct smu_context *smu, uint32_t block_type, + bool gate) +@@ -529,6 +530,47 @@ static int smu_fini_fb_allocations(struct smu_context *smu) + return 0; + } + ++static int smu_override_pcie_parameters(struct smu_context *smu) ++{ ++ struct amdgpu_device *adev = smu->adev; ++ uint32_t pcie_gen = 0, pcie_width = 0, smu_pcie_arg; ++ int ret; ++ ++ if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN4) ++ pcie_gen = 3; ++ else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3) ++ pcie_gen = 2; ++ else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2) ++ pcie_gen = 1; ++ else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1) ++ pcie_gen = 0; ++ ++ /* Bit 31:16: LCLK DPM level. 0 is DPM0, and 1 is DPM1 ++ * Bit 15:8: PCIE GEN, 0 to 3 corresponds to GEN1 to GEN4 ++ * Bit 7:0: PCIE lane width, 1 to 7 corresponds is x1 to x32 ++ */ ++ if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X16) ++ pcie_width = 6; ++ else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X12) ++ pcie_width = 5; ++ else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X8) ++ pcie_width = 4; ++ else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X4) ++ pcie_width = 3; ++ else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X2) ++ pcie_width = 2; ++ else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X1) ++ pcie_width = 1; ++ ++ smu_pcie_arg = (1 << 16) | (pcie_gen << 8) | pcie_width; ++ ret = smu_send_smc_msg_with_param(smu, ++ SMU_MSG_OverridePcieParameters, ++ smu_pcie_arg); ++ if (ret) ++ pr_err("[%s] Attempt to override pcie params failed!\n", __func__); ++ return ret; ++} ++ + static int smu_smc_table_hw_init(struct smu_context *smu, + bool initialize) + { +@@ -616,6 +658,10 @@ static int smu_smc_table_hw_init(struct smu_context *smu, + if (ret) + return ret; + ++ ret = smu_override_pcie_parameters(smu); ++ if (ret) ++ return ret; ++ + ret = smu_notify_display_change(smu); + if (ret) + return ret; +-- +2.17.1 + |