diff options
Diffstat (limited to 'common/recipes-kernel/linux/linux-yocto-4.19.8/1314-drm-amdgpu-powerplay-add-BACO-support-for-vega12.patch')
| -rw-r--r-- | common/recipes-kernel/linux/linux-yocto-4.19.8/1314-drm-amdgpu-powerplay-add-BACO-support-for-vega12.patch | 274 |
1 files changed, 274 insertions, 0 deletions
diff --git a/common/recipes-kernel/linux/linux-yocto-4.19.8/1314-drm-amdgpu-powerplay-add-BACO-support-for-vega12.patch b/common/recipes-kernel/linux/linux-yocto-4.19.8/1314-drm-amdgpu-powerplay-add-BACO-support-for-vega12.patch new file mode 100644 index 00000000..03802b0d --- /dev/null +++ b/common/recipes-kernel/linux/linux-yocto-4.19.8/1314-drm-amdgpu-powerplay-add-BACO-support-for-vega12.patch @@ -0,0 +1,274 @@ +From 58cf0c32f338220e85ec5e922b432a0148e87078 Mon Sep 17 00:00:00 2001 +From: Alex Deucher <alexander.deucher@amd.com> +Date: Sun, 10 Feb 2019 21:46:59 -0500 +Subject: [PATCH 1314/2940] drm/amdgpu/powerplay: add BACO support for vega12 + +This implements BACO (Bus Active, Chip Off) support +for vega12. + +Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> +Signed-off-by: Alex Deucher <alexander.deucher@amd.com> +--- + drivers/gpu/drm/amd/powerplay/hwmgr/Makefile | 3 +- + .../gpu/drm/amd/powerplay/hwmgr/vega12_baco.c | 156 ++++++++++++++++++ + .../gpu/drm/amd/powerplay/hwmgr/vega12_baco.h | 32 ++++ + .../drm/amd/powerplay/hwmgr/vega12_hwmgr.c | 5 + + .../gpu/drm/amd/powerplay/hwmgr/vega12_inc.h | 2 + + 5 files changed, 197 insertions(+), 1 deletion(-) + create mode 100644 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_baco.c + create mode 100644 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_baco.h + +diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/Makefile b/drivers/gpu/drm/amd/powerplay/hwmgr/Makefile +index 0b3c6d1d52e4..d1adf68f4c64 100644 +--- a/drivers/gpu/drm/amd/powerplay/hwmgr/Makefile ++++ b/drivers/gpu/drm/amd/powerplay/hwmgr/Makefile +@@ -35,7 +35,8 @@ HARDWARE_MGR = hwmgr.o processpptables.o \ + vega12_thermal.o \ + pp_overdriver.o smu_helper.o \ + vega20_processpptables.o vega20_hwmgr.o vega20_powertune.o \ +- vega20_thermal.o common_baco.o vega10_baco.o vega20_baco.o ++ vega20_thermal.o common_baco.o vega10_baco.o vega20_baco.o \ ++ vega12_baco.o + + AMD_PP_HWMGR = $(addprefix $(AMD_PP_PATH)/hwmgr/,$(HARDWARE_MGR)) + +diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_baco.c b/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_baco.c +new file mode 100644 +index 000000000000..c2cc15385012 +--- /dev/null ++++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_baco.c +@@ -0,0 +1,156 @@ ++/* ++ * Copyright 2019 Advanced Micro Devices, Inc. ++ * ++ * Permission is hereby granted, free of charge, to any person obtaining a ++ * copy of this software and associated documentation files (the "Software"), ++ * to deal in the Software without restriction, including without limitation ++ * the rights to use, copy, modify, merge, publish, distribute, sublicense, ++ * and/or sell copies of the Software, and to permit persons to whom the ++ * Software is furnished to do so, subject to the following conditions: ++ * ++ * The above copyright notice and this permission notice shall be included in ++ * all copies or substantial portions of the Software. ++ * ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR ++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, ++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL ++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR ++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR ++ * OTHER DEALINGS IN THE SOFTWARE. ++ * ++ */ ++#include "amdgpu.h" ++#include "soc15.h" ++#include "soc15_hw_ip.h" ++#include "vega10_ip_offset.h" ++#include "soc15_common.h" ++#include "vega12_inc.h" ++#include "vega12_ppsmc.h" ++#include "vega12_baco.h" ++ ++static const struct soc15_baco_cmd_entry pre_baco_tbl[] = ++{ ++ { CMD_READMODIFYWRITE, NBIF_HWID, 0, mmBIF_DOORBELL_CNTL_BASE_IDX, mmBIF_DOORBELL_CNTL, BIF_DOORBELL_CNTL__DOORBELL_MONITOR_EN_MASK, BIF_DOORBELL_CNTL__DOORBELL_MONITOR_EN__SHIFT, 0, 0 }, ++ { CMD_WRITE, NBIF_HWID, 0, mmBIF_FB_EN_BASE_IDX, mmBIF_FB_EN, 0, 0, 0, 0 }, ++ { CMD_READMODIFYWRITE, NBIF_HWID, 0, mmRCC_BACO_CNTL_MISC_BASE_IDX, mmBACO_CNTL, BACO_CNTL__BACO_DSTATE_BYPASS_MASK, BACO_CNTL__BACO_DSTATE_BYPASS__SHIFT, 0, 1 }, ++ { CMD_READMODIFYWRITE, NBIF_HWID, 0, mmRCC_BACO_CNTL_MISC_BASE_IDX, mmBACO_CNTL, BACO_CNTL__BACO_RST_INTR_MASK_MASK, BACO_CNTL__BACO_RST_INTR_MASK__SHIFT, 0, 1 } ++}; ++ ++static const struct soc15_baco_cmd_entry enter_baco_tbl[] = ++{ ++ { CMD_WAITFOR, THM_HWID, 0, mmTHM_BACO_CNTL_BASE_IDX, mmTHM_BACO_CNTL, THM_BACO_CNTL__SOC_DOMAIN_IDLE_MASK, THM_BACO_CNTL__SOC_DOMAIN_IDLE__SHIFT, 0xffffffff, 0x80000000 }, ++ { CMD_READMODIFYWRITE, NBIF_HWID, 0, mmRCC_BACO_CNTL_MISC_BASE_IDX, mmBACO_CNTL, BACO_CNTL__BACO_EN_MASK, BACO_CNTL__BACO_EN__SHIFT, 0, 1 }, ++ { CMD_READMODIFYWRITE, NBIF_HWID, 0, mmRCC_BACO_CNTL_MISC_BASE_IDX, mmBACO_CNTL, BACO_CNTL__BACO_BIF_LCLK_SWITCH_MASK, BACO_CNTL__BACO_BIF_LCLK_SWITCH__SHIFT, 0, 1 }, ++ { CMD_READMODIFYWRITE, NBIF_HWID, 0, mmRCC_BACO_CNTL_MISC_BASE_IDX, mmBACO_CNTL, BACO_CNTL__BACO_DUMMY_EN_MASK, BACO_CNTL__BACO_DUMMY_EN__SHIFT, 0, 1 }, ++ { CMD_READMODIFYWRITE, THM_HWID, 0, mmTHM_BACO_CNTL_BASE_IDX, mmTHM_BACO_CNTL, THM_BACO_CNTL__BACO_SOC_VDCI_RESET_MASK, THM_BACO_CNTL__BACO_SOC_VDCI_RESET__SHIFT, 0, 1 }, ++ { CMD_READMODIFYWRITE, THM_HWID, 0, mmTHM_BACO_CNTL_BASE_IDX, mmTHM_BACO_CNTL, THM_BACO_CNTL__BACO_SMNCLK_MUX_MASK, THM_BACO_CNTL__BACO_SMNCLK_MUX__SHIFT, 0, 1 }, ++ { CMD_READMODIFYWRITE, THM_HWID, 0, mmTHM_BACO_CNTL_BASE_IDX, mmTHM_BACO_CNTL, THM_BACO_CNTL__BACO_ISO_EN_MASK, THM_BACO_CNTL__BACO_ISO_EN__SHIFT, 0, 1 }, ++ { CMD_READMODIFYWRITE, THM_HWID, 0, mmTHM_BACO_CNTL_BASE_IDX, mmTHM_BACO_CNTL, THM_BACO_CNTL__BACO_AEB_ISO_EN_MASK, THM_BACO_CNTL__BACO_AEB_ISO_EN__SHIFT, 0, 1 }, ++ { CMD_READMODIFYWRITE, THM_HWID, 0, mmTHM_BACO_CNTL_BASE_IDX, mmTHM_BACO_CNTL, THM_BACO_CNTL__BACO_ANA_ISO_EN_MASK, THM_BACO_CNTL__BACO_ANA_ISO_EN__SHIFT, 0, 1 }, ++ { CMD_READMODIFYWRITE, THM_HWID, 0, mmTHM_BACO_CNTL_BASE_IDX, mmTHM_BACO_CNTL, THM_BACO_CNTL__BACO_SOC_REFCLK_OFF_MASK, THM_BACO_CNTL__BACO_SOC_REFCLK_OFF__SHIFT, 0, 1 }, ++ { CMD_READMODIFYWRITE, NBIF_HWID, 0, mmRCC_BACO_CNTL_MISC_BASE_IDX, mmBACO_CNTL, BACO_CNTL__BACO_POWER_OFF_MASK, BACO_CNTL__BACO_POWER_OFF__SHIFT, 0, 1 }, ++ { CMD_DELAY_MS, 0, 0, 0, 5, 0 }, ++ { CMD_READMODIFYWRITE, THM_HWID, 0, mmTHM_BACO_CNTL_BASE_IDX, mmTHM_BACO_CNTL, THM_BACO_CNTL__BACO_RESET_EN_MASK, THM_BACO_CNTL__BACO_RESET_EN__SHIFT, 0, 1 }, ++ { CMD_READMODIFYWRITE, THM_HWID, 0, mmTHM_BACO_CNTL_BASE_IDX, mmTHM_BACO_CNTL, THM_BACO_CNTL__BACO_PWROKRAW_CNTL_MASK, THM_BACO_CNTL__BACO_PWROKRAW_CNTL__SHIFT, 0, 0 }, ++ { CMD_WAITFOR, NBIF_HWID, 0, mmRCC_BACO_CNTL_MISC_BASE_IDX, mmBACO_CNTL, BACO_CNTL__BACO_MODE_MASK, BACO_CNTL__BACO_MODE__SHIFT, 0xffffffff, 0x100 } ++}; ++ ++static const struct soc15_baco_cmd_entry exit_baco_tbl[] = ++{ ++ { CMD_READMODIFYWRITE, NBIF_HWID, 0, mmRCC_BACO_CNTL_MISC_BASE_IDX, mmBACO_CNTL, BACO_CNTL__BACO_POWER_OFF_MASK, BACO_CNTL__BACO_POWER_OFF__SHIFT, 0, 0 }, ++ { CMD_DELAY_MS, 0, 0, 0, 0, 0, 0, 10, 0 }, ++ { CMD_READMODIFYWRITE, THM_HWID, 0, mmTHM_BACO_CNTL_BASE_IDX, mmTHM_BACO_CNTL, THM_BACO_CNTL__BACO_SOC_REFCLK_OFF_MASK, THM_BACO_CNTL__BACO_SOC_REFCLK_OFF__SHIFT, 0, 0 }, ++ { CMD_READMODIFYWRITE, THM_HWID, 0, mmTHM_BACO_CNTL_BASE_IDX, mmTHM_BACO_CNTL, THM_BACO_CNTL__BACO_ANA_ISO_EN_MASK, THM_BACO_CNTL__BACO_ANA_ISO_EN__SHIFT, 0, 0 }, ++ { CMD_READMODIFYWRITE, THM_HWID, 0, mmTHM_BACO_CNTL_BASE_IDX, mmTHM_BACO_CNTL, THM_BACO_CNTL__BACO_AEB_ISO_EN_MASK, THM_BACO_CNTL__BACO_AEB_ISO_EN__SHIFT, 0, 0 }, ++ { CMD_READMODIFYWRITE, THM_HWID, 0, mmTHM_BACO_CNTL_BASE_IDX, mmTHM_BACO_CNTL, THM_BACO_CNTL__BACO_ISO_EN_MASK, THM_BACO_CNTL__BACO_ISO_EN__SHIFT, 0, 0 }, ++ { CMD_READMODIFYWRITE, THM_HWID, 0, mmTHM_BACO_CNTL_BASE_IDX, mmTHM_BACO_CNTL, THM_BACO_CNTL__BACO_PWROKRAW_CNTL_MASK, THM_BACO_CNTL__BACO_PWROKRAW_CNTL__SHIFT, 0, 1 }, ++ { CMD_READMODIFYWRITE, THM_HWID, 0, mmTHM_BACO_CNTL_BASE_IDX, mmTHM_BACO_CNTL, THM_BACO_CNTL__BACO_SMNCLK_MUX_MASK, THM_BACO_CNTL__BACO_SMNCLK_MUX__SHIFT, 0, 0 }, ++ { CMD_READMODIFYWRITE, THM_HWID, 0, mmTHM_BACO_CNTL_BASE_IDX, mmTHM_BACO_CNTL, THM_BACO_CNTL__BACO_SOC_VDCI_RESET_MASK, THM_BACO_CNTL__BACO_SOC_VDCI_RESET__SHIFT, 0, 0 }, ++ { CMD_READMODIFYWRITE, THM_HWID, 0, mmTHM_BACO_CNTL_BASE_IDX, mmTHM_BACO_CNTL, THM_BACO_CNTL__BACO_EXIT_MASK, THM_BACO_CNTL__BACO_EXIT__SHIFT, 0, 1 }, ++ { CMD_READMODIFYWRITE, THM_HWID, 0, mmTHM_BACO_CNTL_BASE_IDX, mmTHM_BACO_CNTL, THM_BACO_CNTL__BACO_RESET_EN_MASK, THM_BACO_CNTL__BACO_RESET_EN__SHIFT, 0, 0 }, ++ { CMD_WAITFOR, THM_HWID, 0, mmTHM_BACO_CNTL_BASE_IDX, mmTHM_BACO_CNTL, THM_BACO_CNTL__BACO_EXIT_MASK, 0, 0xffffffff, 0 }, ++ { CMD_READMODIFYWRITE, THM_HWID, 0, mmTHM_BACO_CNTL_BASE_IDX, mmTHM_BACO_CNTL, THM_BACO_CNTL__BACO_SB_AXI_FENCE_MASK, THM_BACO_CNTL__BACO_SB_AXI_FENCE__SHIFT, 0, 0 }, ++ { CMD_READMODIFYWRITE, NBIF_HWID, 0, mmRCC_BACO_CNTL_MISC_BASE_IDX, mmBACO_CNTL, BACO_CNTL__BACO_DUMMY_EN_MASK, BACO_CNTL__BACO_DUMMY_EN__SHIFT, 0, 0 }, ++ { CMD_READMODIFYWRITE, NBIF_HWID, 0, mmRCC_BACO_CNTL_MISC_BASE_IDX, mmBACO_CNTL, BACO_CNTL__BACO_BIF_LCLK_SWITCH_MASK, BACO_CNTL__BACO_BIF_LCLK_SWITCH__SHIFT, 0, 0 }, ++ { CMD_READMODIFYWRITE, NBIF_HWID, 0, mmRCC_BACO_CNTL_MISC_BASE_IDX, mmBACO_CNTL, BACO_CNTL__BACO_EN_MASK, BACO_CNTL__BACO_EN__SHIFT, 0, 0 }, ++ { CMD_WAITFOR, NBIF_HWID, 0, mmRCC_BACO_CNTL_MISC_BASE_IDX, mmBACO_CNTL, BACO_CNTL__BACO_MODE_MASK, 0, 0xffffffff, 0 } ++}; ++ ++static const struct soc15_baco_cmd_entry clean_baco_tbl[] = ++{ ++ { CMD_WRITE, NBIF_HWID, 0, mmBIOS_SCRATCH_6_BASE_IDX, mmBIOS_SCRATCH_6, 0, 0, 0, 0 }, ++ { CMD_WRITE, NBIF_HWID, 0, mmBIOS_SCRATCH_7_BASE_IDX, mmBIOS_SCRATCH_7, 0, 0, 0, 0 } ++}; ++ ++int vega12_baco_get_capability(struct pp_hwmgr *hwmgr, bool *cap) ++{ ++ struct amdgpu_device *adev = (struct amdgpu_device *)(hwmgr->adev); ++ uint32_t reg, data; ++ ++ *cap = false; ++ if (!phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_BACO)) ++ return 0; ++ ++ WREG32(0x12074, 0xFFF0003B); ++ data = RREG32(0x12075); ++ ++ if (data == 0x1) { ++ reg = RREG32_SOC15(NBIF, 0, mmRCC_BIF_STRAP0); ++ ++ if (reg & RCC_BIF_STRAP0__STRAP_PX_CAPABLE_MASK) ++ *cap = true; ++ } ++ ++ return 0; ++} ++ ++int vega12_baco_get_state(struct pp_hwmgr *hwmgr, enum BACO_STATE *state) ++{ ++ struct amdgpu_device *adev = (struct amdgpu_device *)(hwmgr->adev); ++ uint32_t reg; ++ ++ reg = RREG32_SOC15(NBIF, 0, mmBACO_CNTL); ++ ++ if (reg & BACO_CNTL__BACO_MODE_MASK) ++ /* gfx has already entered BACO state */ ++ *state = BACO_STATE_IN; ++ else ++ *state = BACO_STATE_OUT; ++ return 0; ++} ++ ++int vega12_baco_set_state(struct pp_hwmgr *hwmgr, enum BACO_STATE state) ++{ ++ enum BACO_STATE cur_state; ++ ++ vega12_baco_get_state(hwmgr, &cur_state); ++ ++ if (cur_state == state) ++ /* aisc already in the target state */ ++ return 0; ++ ++ if (state == BACO_STATE_IN) { ++ if (soc15_baco_program_registers(hwmgr, pre_baco_tbl, ++ ARRAY_SIZE(pre_baco_tbl))) { ++ if (smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_EnterBaco, 0)) ++ return -EINVAL; ++ ++ if (soc15_baco_program_registers(hwmgr, enter_baco_tbl, ++ ARRAY_SIZE(enter_baco_tbl))) ++ return 0; ++ } ++ } else if (state == BACO_STATE_OUT) { ++ /* HW requires at least 20ms between regulator off and on */ ++ msleep(20); ++ /* Execute Hardware BACO exit sequence */ ++ if (soc15_baco_program_registers(hwmgr, exit_baco_tbl, ++ ARRAY_SIZE(exit_baco_tbl))) { ++ if (soc15_baco_program_registers(hwmgr, clean_baco_tbl, ++ ARRAY_SIZE(clean_baco_tbl))) ++ return 0; ++ } ++ } ++ ++ return -EINVAL; ++} +diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_baco.h b/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_baco.h +new file mode 100644 +index 000000000000..457670ee9dda +--- /dev/null ++++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_baco.h +@@ -0,0 +1,32 @@ ++/* ++ * Copyright 2019 Advanced Micro Devices, Inc. ++ * ++ * Permission is hereby granted, free of charge, to any person obtaining a ++ * copy of this software and associated documentation files (the "Software"), ++ * to deal in the Software without restriction, including without limitation ++ * the rights to use, copy, modify, merge, publish, distribute, sublicense, ++ * and/or sell copies of the Software, and to permit persons to whom the ++ * Software is furnished to do so, subject to the following conditions: ++ * ++ * The above copyright notice and this permission notice shall be included in ++ * all copies or substantial portions of the Software. ++ * ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR ++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, ++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL ++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR ++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR ++ * OTHER DEALINGS IN THE SOFTWARE. ++ * ++ */ ++#ifndef __VEGA12_BACO_H__ ++#define __VEGA12_BACO_H__ ++#include "hwmgr.h" ++#include "common_baco.h" ++ ++extern int vega12_baco_get_capability(struct pp_hwmgr *hwmgr, bool *cap); ++extern int vega12_baco_get_state(struct pp_hwmgr *hwmgr, enum BACO_STATE *state); ++extern int vega12_baco_set_state(struct pp_hwmgr *hwmgr, enum BACO_STATE state); ++ ++#endif +diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c +index bdb48e94eff6..b78a6c263627 100644 +--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c ++++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c +@@ -45,6 +45,7 @@ + #include "ppinterrupt.h" + #include "pp_overdriver.h" + #include "pp_thermal.h" ++#include "vega12_baco.h" + + + static int vega12_force_clock_level(struct pp_hwmgr *hwmgr, +@@ -2626,8 +2627,12 @@ static const struct pp_hwmgr_func vega12_hwmgr_funcs = { + .start_thermal_controller = vega12_start_thermal_controller, + .powergate_gfx = vega12_gfx_off_control, + .get_performance_level = vega12_get_performance_level, ++ .get_asic_baco_capability = vega12_baco_get_capability, ++ .get_asic_baco_state = vega12_baco_get_state, ++ .set_asic_baco_state = vega12_baco_set_state, + .get_ppfeature_status = vega12_get_ppfeature_status, + .set_ppfeature_status = vega12_set_ppfeature_status, ++ + }; + + int vega12_hwmgr_init(struct pp_hwmgr *hwmgr) +diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_inc.h b/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_inc.h +index 30b278c50222..e6d9e84059e1 100644 +--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_inc.h ++++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_inc.h +@@ -35,5 +35,7 @@ + #include "asic_reg/gc/gc_9_2_1_sh_mask.h" + + #include "asic_reg/nbio/nbio_6_1_offset.h" ++#include "asic_reg/nbio/nbio_6_1_offset.h" ++#include "asic_reg/nbio/nbio_6_1_sh_mask.h" + + #endif +-- +2.17.1 + |