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Diffstat (limited to 'common/recipes-kernel/linux/linux-yocto-4.19.8/1305-drm-amd-display-set-clocks-to-0-on-suspend-on-dce80.patch')
-rw-r--r--common/recipes-kernel/linux/linux-yocto-4.19.8/1305-drm-amd-display-set-clocks-to-0-on-suspend-on-dce80.patch56
1 files changed, 56 insertions, 0 deletions
diff --git a/common/recipes-kernel/linux/linux-yocto-4.19.8/1305-drm-amd-display-set-clocks-to-0-on-suspend-on-dce80.patch b/common/recipes-kernel/linux/linux-yocto-4.19.8/1305-drm-amd-display-set-clocks-to-0-on-suspend-on-dce80.patch
new file mode 100644
index 00000000..94dd4418
--- /dev/null
+++ b/common/recipes-kernel/linux/linux-yocto-4.19.8/1305-drm-amd-display-set-clocks-to-0-on-suspend-on-dce80.patch
@@ -0,0 +1,56 @@
+From eb1286c5a48d581bb6b4864ad9dfd8a924b7ded8 Mon Sep 17 00:00:00 2001
+From: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+Date: Tue, 5 Feb 2019 14:03:52 -0500
+Subject: [PATCH 1305/2940] drm/amd/display: set clocks to 0 on suspend on
+ dce80
+
+[Why]
+When a dce80 asic was suspended, the clocks were not set to 0.
+Upon resume, the new clock was compared to the existing clock,
+they were found to be the same, and so the clock was not set.
+This resulted in a blackscreen.
+
+[How]
+In atomic commit, check to see if there are any active pipes.
+If no, set clocks to 0
+
+Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+---
+ .../drm/amd/display/dc/dce80/dce80_resource.c | 19 ++++++++++++++++---
+ 1 file changed, 16 insertions(+), 3 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c b/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c
+index 2eca81b5cf2f..c109ace96be9 100644
+--- a/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c
++++ b/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c
+@@ -792,9 +792,22 @@ bool dce80_validate_bandwidth(
+ struct dc *dc,
+ struct dc_state *context)
+ {
+- /* TODO implement when needed but for now hardcode max value*/
+- context->bw.dce.dispclk_khz = 681000;
+- context->bw.dce.yclk_khz = 250000 * MEMORY_TYPE_MULTIPLIER_CZ;
++ int i;
++ bool at_least_one_pipe = false;
++
++ for (i = 0; i < dc->res_pool->pipe_count; i++) {
++ if (context->res_ctx.pipe_ctx[i].stream)
++ at_least_one_pipe = true;
++ }
++
++ if (at_least_one_pipe) {
++ /* TODO implement when needed but for now hardcode max value*/
++ context->bw.dce.dispclk_khz = 681000;
++ context->bw.dce.yclk_khz = 250000 * MEMORY_TYPE_MULTIPLIER_CZ;
++ } else {
++ context->bw.dce.dispclk_khz = 0;
++ context->bw.dce.yclk_khz = 0;
++ }
+
+ return true;
+ }
+--
+2.17.1
+