diff options
Diffstat (limited to 'common/recipes-kernel/linux/linux-yocto-4.19.8/1291-drm-amd-display-PPLIB-Hookup.patch')
-rw-r--r-- | common/recipes-kernel/linux/linux-yocto-4.19.8/1291-drm-amd-display-PPLIB-Hookup.patch | 317 |
1 files changed, 317 insertions, 0 deletions
diff --git a/common/recipes-kernel/linux/linux-yocto-4.19.8/1291-drm-amd-display-PPLIB-Hookup.patch b/common/recipes-kernel/linux/linux-yocto-4.19.8/1291-drm-amd-display-PPLIB-Hookup.patch new file mode 100644 index 00000000..5e30d04e --- /dev/null +++ b/common/recipes-kernel/linux/linux-yocto-4.19.8/1291-drm-amd-display-PPLIB-Hookup.patch @@ -0,0 +1,317 @@ +From 6b1954588100e77dd85d7d59562c8e3b3cf2613f Mon Sep 17 00:00:00 2001 +From: Jun Lei <Jun.Lei@amd.com> +Date: Tue, 15 Jan 2019 10:46:46 -0500 +Subject: [PATCH 1291/2940] drm/amd/display: PPLIB Hookup + +[Why] +Make dml and integration with pplib clearer. + +[How] +Change the way the dml formula is initialized to make its values more +clear. Restructure DC interface with pplib into rv_funcs. +Cap clocks received from pplib. + +Signed-off-by: Jun Lei <Jun.Lei@amd.com> +Signed-off-by: Eryk Brol <eryk.brol@amd.com> +Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> +Acked-by: Leo Li <sunpeng.li@amd.com> +--- + .../amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c | 20 +++++----- + .../gpu/drm/amd/display/dc/calcs/dcn_calcs.c | 2 +- + .../display/dc/dce110/dce110_hw_sequencer.c | 37 ++++++++++++++----- + .../drm/amd/display/dc/dcn10/dcn10_clk_mgr.c | 2 +- + .../drm/amd/display/dc/dcn10/dcn10_resource.c | 6 +-- + drivers/gpu/drm/amd/display/dc/dm_pp_smu.h | 2 + + drivers/gpu/drm/amd/display/dc/dm_services.h | 4 +- + .../drm/amd/display/dc/dm_services_types.h | 2 +- + .../drm/amd/display/dc/dml/display_mode_lib.c | 24 ++++++++++++ + .../drm/amd/display/dc/dml/display_mode_lib.h | 5 +++ + .../gpu/drm/amd/display/dc/inc/core_types.h | 2 +- + 11 files changed, 78 insertions(+), 28 deletions(-) + +diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c +index 19bec697ef9d..2f223289b9bd 100644 +--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c ++++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c +@@ -611,17 +611,17 @@ void pp_rv_set_hard_min_fclk_by_freq(struct pp_smu *pp, int mhz) + pp_funcs->set_hard_min_fclk_by_freq(pp_handle, mhz); + } + +-void dm_pp_get_funcs_rv( ++void dm_pp_get_funcs( + struct dc_context *ctx, +- struct pp_smu_funcs_rv *funcs) ++ struct pp_smu_funcs *funcs) + { +- funcs->pp_smu.dm = ctx; +- funcs->set_display_requirement = pp_rv_set_display_requirement; +- funcs->set_wm_ranges = pp_rv_set_wm_ranges; +- funcs->set_pme_wa_enable = pp_rv_set_pme_wa_enable; +- funcs->set_display_count = pp_rv_set_active_display_count; +- funcs->set_min_deep_sleep_dcfclk = pp_rv_set_min_deep_sleep_dcfclk; +- funcs->set_hard_min_dcfclk_by_freq = pp_rv_set_hard_min_dcefclk_by_freq; +- funcs->set_hard_min_fclk_by_freq = pp_rv_set_hard_min_fclk_by_freq; ++ funcs->rv_funcs.pp_smu.dm = ctx; ++ funcs->rv_funcs.set_display_requirement = pp_rv_set_display_requirement; ++ funcs->rv_funcs.set_wm_ranges = pp_rv_set_wm_ranges; ++ funcs->rv_funcs.set_pme_wa_enable = pp_rv_set_pme_wa_enable; ++ funcs->rv_funcs.set_display_count = pp_rv_set_active_display_count; ++ funcs->rv_funcs.set_min_deep_sleep_dcfclk = pp_rv_set_min_deep_sleep_dcfclk; ++ funcs->rv_funcs.set_hard_min_dcfclk_by_freq = pp_rv_set_hard_min_dcefclk_by_freq; ++ funcs->rv_funcs.set_hard_min_fclk_by_freq = pp_rv_set_hard_min_fclk_by_freq; + } + +diff --git a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c +index 12d1842079ae..2a807b9f77f7 100644 +--- a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c ++++ b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c +@@ -1391,7 +1391,7 @@ void dcn_bw_update_from_pplib(struct dc *dc) + + void dcn_bw_notify_pplib_of_wm_ranges(struct dc *dc) + { +- struct pp_smu_funcs_rv *pp = dc->res_pool->pp_smu; ++ struct pp_smu_funcs_rv *pp = &dc->res_pool->pp_smu->rv_funcs; + struct pp_smu_wm_range_sets ranges = {0}; + int min_fclk_khz, min_dcfclk_khz, socclk_khz; + const int overdrive = 5000000; /* 5 GHz to cover Overdrive */ +diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c +index 702dfe0a2e2b..5a44ff6df0fb 100644 +--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c ++++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c +@@ -935,13 +935,31 @@ void hwss_edp_backlight_control( + edp_receiver_ready_T9(link); + } + ++// Static helper function which calls the correct function ++// based on pp_smu version ++static void set_pme_wa_enable_by_version(struct dc *dc) ++{ ++ struct pp_smu_funcs *pp_smu = NULL; ++ ++ if (dc->res_pool->pp_smu) ++ pp_smu = dc->res_pool->pp_smu; ++ ++ if (pp_smu) { ++ if (pp_smu->ctx.ver == PP_SMU_VER_RV && pp_smu->rv_funcs.set_pme_wa_enable) ++ pp_smu->rv_funcs.set_pme_wa_enable(&(pp_smu->ctx)); ++ } ++} ++ + void dce110_enable_audio_stream(struct pipe_ctx *pipe_ctx) + { +- struct dc *core_dc = pipe_ctx->stream->ctx->dc; + /* notify audio driver for audio modes of monitor */ +- struct pp_smu_funcs_rv *pp_smu = core_dc->res_pool->pp_smu; ++ struct dc *core_dc = pipe_ctx->stream->ctx->dc; ++ struct pp_smu_funcs *pp_smu = NULL; + unsigned int i, num_audio = 1; + ++ if (core_dc->res_pool->pp_smu) ++ pp_smu = core_dc->res_pool->pp_smu; ++ + if (pipe_ctx->stream_res.audio) { + for (i = 0; i < MAX_PIPES; i++) { + /*current_state not updated yet*/ +@@ -951,9 +969,9 @@ void dce110_enable_audio_stream(struct pipe_ctx *pipe_ctx) + + pipe_ctx->stream_res.audio->funcs->az_enable(pipe_ctx->stream_res.audio); + +- if (num_audio >= 1 && pp_smu != NULL && pp_smu->set_pme_wa_enable != NULL) ++ if (num_audio >= 1 && pp_smu != NULL) + /*this is the first audio. apply the PME w/a in order to wake AZ from D3*/ +- pp_smu->set_pme_wa_enable(&pp_smu->pp_smu); ++ set_pme_wa_enable_by_version(core_dc); + /* un-mute audio */ + /* TODO: audio should be per stream rather than per link */ + pipe_ctx->stream_res.stream_enc->funcs->audio_mute_control( +@@ -964,17 +982,18 @@ void dce110_enable_audio_stream(struct pipe_ctx *pipe_ctx) + void dce110_disable_audio_stream(struct pipe_ctx *pipe_ctx, int option) + { + struct dc *dc = pipe_ctx->stream->ctx->dc; ++ struct pp_smu_funcs *pp_smu = NULL; + + pipe_ctx->stream_res.stream_enc->funcs->audio_mute_control( + pipe_ctx->stream_res.stream_enc, true); + if (pipe_ctx->stream_res.audio) { +- struct pp_smu_funcs_rv *pp_smu = dc->res_pool->pp_smu; ++ if (dc->res_pool->pp_smu) ++ pp_smu = dc->res_pool->pp_smu; + + if (option != KEEP_ACQUIRED_RESOURCE || +- !dc->debug.az_endpoint_mute_only) { ++ !dc->debug.az_endpoint_mute_only) + /*only disalbe az_endpoint if power down or free*/ + pipe_ctx->stream_res.audio->funcs->az_disable(pipe_ctx->stream_res.audio); +- } + + if (dc_is_dp_signal(pipe_ctx->stream->signal)) + pipe_ctx->stream_res.stream_enc->funcs->dp_audio_disable( +@@ -989,9 +1008,9 @@ void dce110_disable_audio_stream(struct pipe_ctx *pipe_ctx, int option) + update_audio_usage(&dc->current_state->res_ctx, dc->res_pool, pipe_ctx->stream_res.audio, false); + pipe_ctx->stream_res.audio = NULL; + } +- if (pp_smu != NULL && pp_smu->set_pme_wa_enable != NULL) ++ if (pp_smu != NULL) + /*this is the first audio. apply the PME w/a in order to wake AZ from D3*/ +- pp_smu->set_pme_wa_enable(&pp_smu->pp_smu); ++ set_pme_wa_enable_by_version(dc); + + /* TODO: notify audio driver for if audio modes list changed + * add audio mode list change flag */ +diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_clk_mgr.c +index 451c9c62c0c2..1f3eaa20a0de 100644 +--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_clk_mgr.c ++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_clk_mgr.c +@@ -171,7 +171,7 @@ static void dcn1_update_clocks(struct clk_mgr *clk_mgr, + struct pp_smu_display_requirement_rv *smu_req_cur = + &dc->res_pool->pp_smu_req; + struct pp_smu_display_requirement_rv smu_req = *smu_req_cur; +- struct pp_smu_funcs_rv *pp_smu = dc->res_pool->pp_smu; ++ struct pp_smu_funcs_rv *pp_smu = &dc->res_pool->pp_smu->rv_funcs; + bool send_request_to_increase = false; + bool send_request_to_lower = false; + int display_count; +diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c +index 09d74070a49b..dd8d189d17c9 100644 +--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c ++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c +@@ -848,14 +848,14 @@ void dcn10_clock_source_destroy(struct clock_source **clk_src) + *clk_src = NULL; + } + +-static struct pp_smu_funcs_rv *dcn10_pp_smu_create(struct dc_context *ctx) ++static struct pp_smu_funcs *dcn10_pp_smu_create(struct dc_context *ctx) + { +- struct pp_smu_funcs_rv *pp_smu = kzalloc(sizeof(*pp_smu), GFP_KERNEL); ++ struct pp_smu_funcs *pp_smu = kzalloc(sizeof(*pp_smu), GFP_KERNEL); + + if (!pp_smu) + return pp_smu; + +- dm_pp_get_funcs_rv(ctx, pp_smu); ++ dm_pp_get_funcs(ctx, pp_smu); + return pp_smu; + } + +diff --git a/drivers/gpu/drm/amd/display/dc/dm_pp_smu.h b/drivers/gpu/drm/amd/display/dc/dm_pp_smu.h +index 9c5ee2605504..fe78f32819ed 100644 +--- a/drivers/gpu/drm/amd/display/dc/dm_pp_smu.h ++++ b/drivers/gpu/drm/amd/display/dc/dm_pp_smu.h +@@ -30,6 +30,8 @@ + * interface to PPLIB/SMU to setup clocks and pstate requirements on SoC + */ + ++typedef bool BOOLEAN; ++ + enum pp_smu_ver { + /* + * PP_SMU_INTERFACE_X should be interpreted as the interface defined +diff --git a/drivers/gpu/drm/amd/display/dc/dm_services.h b/drivers/gpu/drm/amd/display/dc/dm_services.h +index 1961cc6d9143..56832425a4d5 100644 +--- a/drivers/gpu/drm/amd/display/dc/dm_services.h ++++ b/drivers/gpu/drm/amd/display/dc/dm_services.h +@@ -223,8 +223,8 @@ bool dm_pp_notify_wm_clock_changes( + const struct dc_context *ctx, + struct dm_pp_wm_sets_with_clock_ranges *wm_with_clock_ranges); + +-void dm_pp_get_funcs_rv(struct dc_context *ctx, +- struct pp_smu_funcs_rv *funcs); ++void dm_pp_get_funcs(struct dc_context *ctx, ++ struct pp_smu_funcs *funcs); + + /* DAL calls this function to notify PP about completion of Mode Set. + * For PP it means that current DCE clocks are those which were returned +diff --git a/drivers/gpu/drm/amd/display/dc/dm_services_types.h b/drivers/gpu/drm/amd/display/dc/dm_services_types.h +index 77200711abbe..a3d1be20dd9d 100644 +--- a/drivers/gpu/drm/amd/display/dc/dm_services_types.h ++++ b/drivers/gpu/drm/amd/display/dc/dm_services_types.h +@@ -29,7 +29,7 @@ + #include "os_types.h" + #include "dc_types.h" + +-struct pp_smu_funcs_rv; ++struct pp_smu_funcs; + + struct dm_pp_clock_range { + int min_khz; +diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_mode_lib.c b/drivers/gpu/drm/amd/display/dc/dml/display_mode_lib.c +index d303b789adfe..a2bd3a651781 100644 +--- a/drivers/gpu/drm/amd/display/dc/dml/display_mode_lib.c ++++ b/drivers/gpu/drm/amd/display/dc/dml/display_mode_lib.c +@@ -29,6 +29,12 @@ + extern const struct _vcs_dpi_ip_params_st dcn1_0_ip; + extern const struct _vcs_dpi_soc_bounding_box_st dcn1_0_soc; + ++static void set_soc_bounding_box_v2(struct display_mode_lib *lib, ++ const struct _vcs_dpi_soc_bounding_box_st *soc_bb) ++{ ++ lib->soc = *soc_bb; ++} ++ + static void set_soc_bounding_box(struct _vcs_dpi_soc_bounding_box_st *soc, enum dml_project project) + { + switch (project) { +@@ -41,6 +47,12 @@ static void set_soc_bounding_box(struct _vcs_dpi_soc_bounding_box_st *soc, enum + } + } + ++static void set_ip_params_v2(struct display_mode_lib *lib, ++ const struct _vcs_dpi_ip_params_st *ip_params) ++{ ++ lib->ip = *ip_params; ++} ++ + static void set_ip_params(struct _vcs_dpi_ip_params_st *ip, enum dml_project project) + { + switch (project) { +@@ -62,6 +74,18 @@ void dml_init_instance(struct display_mode_lib *lib, enum dml_project project) + } + } + ++void dml_init_instance_v2(struct display_mode_lib *lib, ++ const struct _vcs_dpi_soc_bounding_box_st *soc_bb, ++ const struct _vcs_dpi_ip_params_st *ip_params, ++ enum dml_project project) ++{ ++ if (lib->project != project) { ++ set_soc_bounding_box_v2(lib, soc_bb); ++ set_ip_params_v2(lib, ip_params); ++ lib->project = project; ++ } ++} ++ + const char *dml_get_status_message(enum dm_validation_status status) + { + switch (status) { +diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_mode_lib.h b/drivers/gpu/drm/amd/display/dc/dml/display_mode_lib.h +index a730e0209c05..93c0197ff272 100644 +--- a/drivers/gpu/drm/amd/display/dc/dml/display_mode_lib.h ++++ b/drivers/gpu/drm/amd/display/dc/dml/display_mode_lib.h +@@ -43,6 +43,11 @@ struct display_mode_lib { + + void dml_init_instance(struct display_mode_lib *lib, enum dml_project project); + ++void dml_init_instance_v2(struct display_mode_lib *lib, ++ const struct _vcs_dpi_soc_bounding_box_st *soc_bb, ++ const struct _vcs_dpi_ip_params_st *ip_params, ++ enum dml_project project); ++ + const char *dml_get_status_message(enum dm_validation_status status); + + #endif +diff --git a/drivers/gpu/drm/amd/display/dc/inc/core_types.h b/drivers/gpu/drm/amd/display/dc/inc/core_types.h +index 30834601f39f..ca3d08524221 100644 +--- a/drivers/gpu/drm/amd/display/dc/inc/core_types.h ++++ b/drivers/gpu/drm/amd/display/dc/inc/core_types.h +@@ -144,7 +144,7 @@ struct resource_pool { + struct stream_encoder *stream_enc[MAX_PIPES * 2]; + struct hubbub *hubbub; + struct mpc *mpc; +- struct pp_smu_funcs_rv *pp_smu; ++ struct pp_smu_funcs *pp_smu; + struct pp_smu_display_requirement_rv pp_smu_req; + struct dce_aux *engines[MAX_PIPES]; + struct dce_i2c_hw *hw_i2cs[MAX_PIPES]; +-- +2.17.1 + |