diff options
Diffstat (limited to 'common/recipes-kernel/linux/linux-yocto-4.19.8/1287-drm-powerplay-print-current-clock-level-when-dpm-is-.patch')
| -rw-r--r-- | common/recipes-kernel/linux/linux-yocto-4.19.8/1287-drm-powerplay-print-current-clock-level-when-dpm-is-.patch | 135 |
1 files changed, 135 insertions, 0 deletions
diff --git a/common/recipes-kernel/linux/linux-yocto-4.19.8/1287-drm-powerplay-print-current-clock-level-when-dpm-is-.patch b/common/recipes-kernel/linux/linux-yocto-4.19.8/1287-drm-powerplay-print-current-clock-level-when-dpm-is-.patch new file mode 100644 index 00000000..e3ca9f1f --- /dev/null +++ b/common/recipes-kernel/linux/linux-yocto-4.19.8/1287-drm-powerplay-print-current-clock-level-when-dpm-is-.patch @@ -0,0 +1,135 @@ +From 0e27716f1d3ed3f10d0e144efea08cd11d2567d7 Mon Sep 17 00:00:00 2001 +From: shaoyunl <shaoyun.liu@amd.com> +Date: Tue, 19 Feb 2019 16:02:11 -0500 +Subject: [PATCH 1287/2940] drm/powerplay: print current clock level when dpm + is disabled on vg20 + +When DPM for the specific clock is disabled, driver should still print out +current clock info for rocm-smi support on vega20 + +Change-Id: I8669c77bf153caa2cd63a575802eb58747151239 +Signed-off-by: shaoyunl <shaoyun.liu@amd.com> +Reviewed-by: Eric Huang <JinhuiEric.Huang@amd.com> +--- + .../drm/amd/powerplay/hwmgr/vega20_hwmgr.c | 56 +++++++++---------- + 1 file changed, 28 insertions(+), 28 deletions(-) + +diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c +index aad79affb081..c95e0f35ed7f 100644 +--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c ++++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c +@@ -2641,9 +2641,8 @@ static int vega20_get_sclks(struct pp_hwmgr *hwmgr, + struct vega20_single_dpm_table *dpm_table = &(data->dpm_table.gfx_table); + int i, count; + +- PP_ASSERT_WITH_CODE(data->smu_features[GNLD_DPM_GFXCLK].enabled, +- "[GetSclks]: gfxclk dpm not enabled!\n", +- return -EPERM); ++ if (!data->smu_features[GNLD_DPM_GFXCLK].enabled) ++ return -1; + + count = (dpm_table->count > MAX_NUM_CLOCKS) ? MAX_NUM_CLOCKS : dpm_table->count; + clocks->num_levels = count; +@@ -2670,9 +2669,8 @@ static int vega20_get_memclocks(struct pp_hwmgr *hwmgr, + struct vega20_single_dpm_table *dpm_table = &(data->dpm_table.mem_table); + int i, count; + +- PP_ASSERT_WITH_CODE(data->smu_features[GNLD_DPM_UCLK].enabled, +- "[GetMclks]: uclk dpm not enabled!\n", +- return -EPERM); ++ if (!data->smu_features[GNLD_DPM_UCLK].enabled) ++ return -1; + + count = (dpm_table->count > MAX_NUM_CLOCKS) ? MAX_NUM_CLOCKS : dpm_table->count; + clocks->num_levels = data->mclk_latency_table.count = count; +@@ -2696,9 +2694,8 @@ static int vega20_get_dcefclocks(struct pp_hwmgr *hwmgr, + struct vega20_single_dpm_table *dpm_table = &(data->dpm_table.dcef_table); + int i, count; + +- PP_ASSERT_WITH_CODE(data->smu_features[GNLD_DPM_DCEFCLK].enabled, +- "[GetDcfclocks]: dcefclk dpm not enabled!\n", +- return -EPERM); ++ if (!data->smu_features[GNLD_DPM_DCEFCLK].enabled) ++ return -1; + + count = (dpm_table->count > MAX_NUM_CLOCKS) ? MAX_NUM_CLOCKS : dpm_table->count; + clocks->num_levels = count; +@@ -2719,9 +2716,8 @@ static int vega20_get_socclocks(struct pp_hwmgr *hwmgr, + struct vega20_single_dpm_table *dpm_table = &(data->dpm_table.soc_table); + int i, count; + +- PP_ASSERT_WITH_CODE(data->smu_features[GNLD_DPM_SOCCLK].enabled, +- "[GetSocclks]: socclk dpm not enabled!\n", +- return -EPERM); ++ if (!data->smu_features[GNLD_DPM_SOCCLK].enabled) ++ return -1; + + count = (dpm_table->count > MAX_NUM_CLOCKS) ? MAX_NUM_CLOCKS : dpm_table->count; + clocks->num_levels = count; +@@ -3137,10 +3133,11 @@ static int vega20_print_clock_levels(struct pp_hwmgr *hwmgr, + "Attempt to get current gfx clk Failed!", + return ret); + +- ret = vega20_get_sclks(hwmgr, &clocks); +- PP_ASSERT_WITH_CODE(!ret, +- "Attempt to get gfx clk levels Failed!", +- return ret); ++ if (vega20_get_sclks(hwmgr, &clocks)) { ++ size += sprintf(buf + size, "0: %uMhz * (DPM disabled)\n", ++ now / 100); ++ break; ++ } + + for (i = 0; i < clocks.num_levels; i++) + size += sprintf(buf + size, "%d: %uMhz %s\n", +@@ -3154,10 +3151,11 @@ static int vega20_print_clock_levels(struct pp_hwmgr *hwmgr, + "Attempt to get current mclk freq Failed!", + return ret); + +- ret = vega20_get_memclocks(hwmgr, &clocks); +- PP_ASSERT_WITH_CODE(!ret, +- "Attempt to get memory clk levels Failed!", +- return ret); ++ if (vega20_get_memclocks(hwmgr, &clocks)) { ++ size += sprintf(buf + size, "0: %uMhz * (DPM disabled)\n", ++ now / 100); ++ break; ++ } + + for (i = 0; i < clocks.num_levels; i++) + size += sprintf(buf + size, "%d: %uMhz %s\n", +@@ -3171,10 +3169,11 @@ static int vega20_print_clock_levels(struct pp_hwmgr *hwmgr, + "Attempt to get current socclk freq Failed!", + return ret); + +- ret = vega20_get_socclocks(hwmgr, &clocks); +- PP_ASSERT_WITH_CODE(!ret, +- "Attempt to get soc clk levels Failed!", +- return ret); ++ if (vega20_get_socclocks(hwmgr, &clocks)) { ++ size += sprintf(buf + size, "0: %uMhz * (DPM disabled)\n", ++ now / 100); ++ break; ++ } + + for (i = 0; i < clocks.num_levels; i++) + size += sprintf(buf + size, "%d: %uMhz %s\n", +@@ -3200,10 +3199,11 @@ static int vega20_print_clock_levels(struct pp_hwmgr *hwmgr, + "Attempt to get current dcefclk freq Failed!", + return ret); + +- ret = vega20_get_dcefclocks(hwmgr, &clocks); +- PP_ASSERT_WITH_CODE(!ret, +- "Attempt to get dcefclk levels Failed!", +- return ret); ++ if (vega20_get_dcefclocks(hwmgr, &clocks)) { ++ size += sprintf(buf + size, "0: %uMhz * (DPM disabled)\n", ++ now / 100); ++ break; ++ } + + for (i = 0; i < clocks.num_levels; i++) + size += sprintf(buf + size, "%d: %uMhz %s\n", +-- +2.17.1 + |