diff options
Diffstat (limited to 'common/recipes-kernel/linux/linux-yocto-4.19.8/1252-drm-amdgpu-Update-sdma-golden-setting-for-vega20.patch')
| -rw-r--r-- | common/recipes-kernel/linux/linux-yocto-4.19.8/1252-drm-amdgpu-Update-sdma-golden-setting-for-vega20.patch | 40 |
1 files changed, 40 insertions, 0 deletions
diff --git a/common/recipes-kernel/linux/linux-yocto-4.19.8/1252-drm-amdgpu-Update-sdma-golden-setting-for-vega20.patch b/common/recipes-kernel/linux/linux-yocto-4.19.8/1252-drm-amdgpu-Update-sdma-golden-setting-for-vega20.patch new file mode 100644 index 00000000..97829dd7 --- /dev/null +++ b/common/recipes-kernel/linux/linux-yocto-4.19.8/1252-drm-amdgpu-Update-sdma-golden-setting-for-vega20.patch @@ -0,0 +1,40 @@ +From eb80724621907c265655f94eda9720aebd2455e8 Mon Sep 17 00:00:00 2001 +From: shaoyunl <shaoyun.liu@amd.com> +Date: Fri, 15 Feb 2019 11:05:04 -0500 +Subject: [PATCH 1252/2940] drm/amdgpu: Update sdma golden setting for vega20 + +According to hardware engineer, WRITE_BURST_LENGTH [9:8] in register +SDMA0_CHICKEN_BITS need to change to 3 for better performance + +Change-Id: I32121ac19a62c0794b43755078e89d447724bf07 +Signed-off-by: shaoyunl <shaoyun.liu@amd.com> +Acked-by: Alex Deucher <alexander.deucher@amd.com> +--- + drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c +index f26cdecb8dfa..d6547a093e67 100644 +--- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c ++++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c +@@ -128,7 +128,7 @@ static const struct soc15_reg_golden golden_settings_sdma0_4_2_init[] = { + + static const struct soc15_reg_golden golden_settings_sdma0_4_2[] = + { +- SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CHICKEN_BITS, 0xfe931f07, 0x02831d07), ++ SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CHICKEN_BITS, 0xfe931f07, 0x02831f07), + SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CLK_CTRL, 0xffffffff, 0x3f000100), + SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0000773f, 0x00004002), + SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002), +@@ -158,7 +158,7 @@ static const struct soc15_reg_golden golden_settings_sdma0_4_2[] = + }; + + static const struct soc15_reg_golden golden_settings_sdma1_4_2[] = { +- SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CHICKEN_BITS, 0xfe931f07, 0x02831d07), ++ SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CHICKEN_BITS, 0xfe931f07, 0x02831f07), + SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CLK_CTRL, 0xffffffff, 0x3f000100), + SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG, 0x0000773f, 0x00004002), + SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002), +-- +2.17.1 + |