diff options
Diffstat (limited to 'common/recipes-kernel/linux/linux-yocto-4.19.8/1231-drm-amd-display-add-n_vid_mul-and-half-pix_rate-for-.patch')
| -rw-r--r-- | common/recipes-kernel/linux/linux-yocto-4.19.8/1231-drm-amd-display-add-n_vid_mul-and-half-pix_rate-for-.patch | 84 |
1 files changed, 84 insertions, 0 deletions
diff --git a/common/recipes-kernel/linux/linux-yocto-4.19.8/1231-drm-amd-display-add-n_vid_mul-and-half-pix_rate-for-.patch b/common/recipes-kernel/linux/linux-yocto-4.19.8/1231-drm-amd-display-add-n_vid_mul-and-half-pix_rate-for-.patch new file mode 100644 index 00000000..719abbca --- /dev/null +++ b/common/recipes-kernel/linux/linux-yocto-4.19.8/1231-drm-amd-display-add-n_vid_mul-and-half-pix_rate-for-.patch @@ -0,0 +1,84 @@ +From 0b200fd708d0b758e6609a6cec68b879b0a8d43e Mon Sep 17 00:00:00 2001 +From: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> +Date: Mon, 14 Jan 2019 15:19:44 -0500 +Subject: [PATCH 1231/2940] drm/amd/display: add n_vid_mul and half pix_rate + for odm + +Dp needs half container rate to properly support odm + +Change-Id: I5a3053c10f54461c5eefc99a44920abfb3d8900e +Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> +Reviewed-by: Nikola Cornij <Nikola.Cornij@amd.com> +Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> +--- + .../gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c | 4 ++-- + drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c | 7 +++++-- + drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h | 2 +- + 3 files changed, 8 insertions(+), 5 deletions(-) + +diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c +index 0c92f33e35f4..0dc3f06bc90e 100644 +--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c ++++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c +@@ -1032,8 +1032,7 @@ void dce110_unblank_stream(struct pipe_ctx *pipe_ctx, + struct dc_link *link = stream->link; + + /* only 3 items below are used by unblank */ +- params.pixel_clk_khz = +- pipe_ctx->stream->timing.pix_clk_100hz / 10; ++ params.pixel_clk_khz = pipe_ctx->stream->timing.pix_clk_100hz / 10; + params.link_settings.link_rate = link_settings->link_rate; + + if (dc_is_dp_signal(pipe_ctx->stream->signal)) +@@ -1043,6 +1042,7 @@ void dce110_unblank_stream(struct pipe_ctx *pipe_ctx, + link->dc->hwss.edp_backlight_control(link, true); + } + } ++ + void dce110_blank_stream(struct pipe_ctx *pipe_ctx) + { + struct dc_stream_state *stream = pipe_ctx->stream; +diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c +index 1dbd1d3999e6..2f78a84f0dcb 100644 +--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c ++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c +@@ -390,7 +390,7 @@ void optc1_program_timing( + + h_div_2 = optc1_is_two_pixels_per_containter(&patched_crtc_timing); + REG_UPDATE(OTG_H_TIMING_CNTL, +- OTG_H_TIMING_DIV_BY2, h_div_2); ++ OTG_H_TIMING_DIV_BY2, h_div_2 || optc1->comb_opp_id != 0xf); + + } + +@@ -1531,10 +1531,13 @@ void dcn10_timing_generator_init(struct optc *optc1) + optc1->min_v_blank_interlace = 5; + optc1->min_h_sync_width = 8; + optc1->min_v_sync_width = 1; ++ optc1->comb_opp_id = 0xf; + } + + bool optc1_is_two_pixels_per_containter(const struct dc_crtc_timing *timing) + { +- return timing->pixel_encoding == PIXEL_ENCODING_YCBCR420; ++ bool two_pix = timing->pixel_encoding == PIXEL_ENCODING_YCBCR420; ++ ++ return two_pix; + } + +diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h +index 8a4e3e37e894..24452f11c598 100644 +--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h ++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h +@@ -435,7 +435,7 @@ struct optc { + const struct dcn_optc_shift *tg_shift; + const struct dcn_optc_mask *tg_mask; + +- enum controller_id controller_id; ++ int comb_opp_id; + + uint32_t max_h_total; + uint32_t max_v_total; +-- +2.17.1 + |