diff options
Diffstat (limited to 'common/recipes-kernel/linux/linux-yocto-4.19.8/1154-drm-amd-powerplay-support-Vega10-retrieving-and-sett.patch')
| -rw-r--r-- | common/recipes-kernel/linux/linux-yocto-4.19.8/1154-drm-amd-powerplay-support-Vega10-retrieving-and-sett.patch | 139 |
1 files changed, 139 insertions, 0 deletions
diff --git a/common/recipes-kernel/linux/linux-yocto-4.19.8/1154-drm-amd-powerplay-support-Vega10-retrieving-and-sett.patch b/common/recipes-kernel/linux/linux-yocto-4.19.8/1154-drm-amd-powerplay-support-Vega10-retrieving-and-sett.patch new file mode 100644 index 00000000..d23d5ef9 --- /dev/null +++ b/common/recipes-kernel/linux/linux-yocto-4.19.8/1154-drm-amd-powerplay-support-Vega10-retrieving-and-sett.patch @@ -0,0 +1,139 @@ +From 0c529e48014194b4c248a0fdf868984efb5af5d2 Mon Sep 17 00:00:00 2001 +From: Evan Quan <evan.quan@amd.com> +Date: Fri, 25 Jan 2019 14:11:31 +0800 +Subject: [PATCH 1154/2940] drm/amd/powerplay: support Vega10 retrieving and + setting ppfeatures + +Enable retrieving and setting ppfeatures on Vega10. + +Signed-off-by: Evan Quan <evan.quan@amd.com> +Reviewed-by: Alex Deucher <alexander.deucher@amd.com> +Signed-off-by: Alex Deucher <alexander.deucher@amd.com> +Signed-off-by: Chaudhary Amit Kumar <Chaudharyamit.Kumar@amd.com> +--- + .../drm/amd/powerplay/hwmgr/vega10_hwmgr.c | 102 ++++++++++++++++++ + 1 file changed, 102 insertions(+) + +diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c +index 8c1871907c6f..0a5f7df3acc2 100644 +--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c ++++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c +@@ -4323,6 +4323,105 @@ static int vega10_set_watermarks_for_clocks_ranges(struct pp_hwmgr *hwmgr, + return result; + } + ++static int vega10_get_ppfeature_status(struct pp_hwmgr *hwmgr, char *buf) ++{ ++ static const char *ppfeature_name[] = { ++ "DPM_PREFETCHER", ++ "GFXCLK_DPM", ++ "UCLK_DPM", ++ "SOCCLK_DPM", ++ "UVD_DPM", ++ "VCE_DPM", ++ "ULV", ++ "MP0CLK_DPM", ++ "LINK_DPM", ++ "DCEFCLK_DPM", ++ "AVFS", ++ "GFXCLK_DS", ++ "SOCCLK_DS", ++ "LCLK_DS", ++ "PPT", ++ "TDC", ++ "THERMAL", ++ "GFX_PER_CU_CG", ++ "RM", ++ "DCEFCLK_DS", ++ "ACDC", ++ "VR0HOT", ++ "VR1HOT", ++ "FW_CTF", ++ "LED_DISPLAY", ++ "FAN_CONTROL", ++ "FAST_PPT", ++ "DIDT", ++ "ACG", ++ "PCC_LIMIT"}; ++ static const char *output_title[] = { ++ "FEATURES", ++ "BITMASK", ++ "ENABLEMENT"}; ++ uint64_t features_enabled; ++ int i; ++ int ret = 0; ++ int size = 0; ++ ++ ret = vega10_get_enabled_smc_features(hwmgr, &features_enabled); ++ PP_ASSERT_WITH_CODE(!ret, ++ "[EnableAllSmuFeatures] Failed to get enabled smc features!", ++ return ret); ++ ++ size += sprintf(buf + size, "Current ppfeatures: 0x%016llx\n", features_enabled); ++ size += sprintf(buf + size, "%-19s %-22s %s\n", ++ output_title[0], ++ output_title[1], ++ output_title[2]); ++ for (i = 0; i < GNLD_FEATURES_MAX; i++) { ++ size += sprintf(buf + size, "%-19s 0x%016llx %6s\n", ++ ppfeature_name[i], ++ 1ULL << i, ++ (features_enabled & (1ULL << i)) ? "Y" : "N"); ++ } ++ ++ return size; ++} ++ ++static int vega10_set_ppfeature_status(struct pp_hwmgr *hwmgr, uint64_t new_ppfeature_masks) ++{ ++ uint64_t features_enabled; ++ uint64_t features_to_enable; ++ uint64_t features_to_disable; ++ int ret = 0; ++ ++ if (new_ppfeature_masks >= (1ULL << GNLD_FEATURES_MAX)) ++ return -EINVAL; ++ ++ ret = vega10_get_enabled_smc_features(hwmgr, &features_enabled); ++ if (ret) ++ return ret; ++ ++ features_to_disable = ++ (features_enabled ^ new_ppfeature_masks) & features_enabled; ++ features_to_enable = ++ (features_enabled ^ new_ppfeature_masks) ^ features_to_disable; ++ ++ pr_debug("features_to_disable 0x%llx\n", features_to_disable); ++ pr_debug("features_to_enable 0x%llx\n", features_to_enable); ++ ++ if (features_to_disable) { ++ ret = vega10_enable_smc_features(hwmgr, false, features_to_disable); ++ if (ret) ++ return ret; ++ } ++ ++ if (features_to_enable) { ++ ret = vega10_enable_smc_features(hwmgr, true, features_to_enable); ++ if (ret) ++ return ret; ++ } ++ ++ return 0; ++} ++ + static int vega10_print_clock_levels(struct pp_hwmgr *hwmgr, + enum pp_clock_type type, char *buf) + { +@@ -5067,6 +5166,9 @@ static const struct pp_hwmgr_func vega10_hwmgr_funcs = { + .get_asic_baco_capability = vega10_baco_get_capability, + .get_asic_baco_state = vega10_baco_get_state, + .set_asic_baco_state = vega10_baco_set_state, ++ .get_ppfeature_status = vega10_get_ppfeature_status, ++ .set_ppfeature_status = vega10_set_ppfeature_status, ++ + }; + + int vega10_hwmgr_init(struct pp_hwmgr *hwmgr) +-- +2.17.1 + |