diff options
Diffstat (limited to 'common/recipes-kernel/linux/linux-yocto-4.19.8/1123-drm-amd-powerplay-fit-the-SOC-clock-also-to-the-new-.patch')
| -rw-r--r-- | common/recipes-kernel/linux/linux-yocto-4.19.8/1123-drm-amd-powerplay-fit-the-SOC-clock-also-to-the-new-.patch | 89 |
1 files changed, 89 insertions, 0 deletions
diff --git a/common/recipes-kernel/linux/linux-yocto-4.19.8/1123-drm-amd-powerplay-fit-the-SOC-clock-also-to-the-new-.patch b/common/recipes-kernel/linux/linux-yocto-4.19.8/1123-drm-amd-powerplay-fit-the-SOC-clock-also-to-the-new-.patch new file mode 100644 index 00000000..47827d58 --- /dev/null +++ b/common/recipes-kernel/linux/linux-yocto-4.19.8/1123-drm-amd-powerplay-fit-the-SOC-clock-also-to-the-new-.patch @@ -0,0 +1,89 @@ +From f48a04d755f867fbeeabac2578b9213509e1d756 Mon Sep 17 00:00:00 2001 +From: Evan Quan <evan.quan@amd.com> +Date: Mon, 21 Jan 2019 14:05:37 +0800 +Subject: [PATCH 1123/2940] drm/amd/powerplay: fit the SOC clock also to the + new performance level + +The SOC clock needs also to fit the new performance level. + +Signed-off-by: Evan Quan <evan.quan@amd.com> +Acked-by: Alex Deucher <alexander.deucher@amd.com> +Signed-off-by: Alex Deucher <alexander.deucher@amd.com> +--- + .../drm/amd/powerplay/hwmgr/vega20_hwmgr.c | 37 +++++++++++++++++++ + 1 file changed, 37 insertions(+) + +diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c +index 8c1fa985c7d4..60a22d8da7f0 100644 +--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c ++++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c +@@ -2170,6 +2170,12 @@ static int vega20_force_dpm_highest(struct pp_hwmgr *hwmgr) + data->dpm_table.mem_table.dpm_state.soft_max_level = + data->dpm_table.mem_table.dpm_levels[soft_level].value; + ++ soft_level = vega20_find_highest_dpm_level(&(data->dpm_table.soc_table)); ++ ++ data->dpm_table.soc_table.dpm_state.soft_min_level = ++ data->dpm_table.soc_table.dpm_state.soft_max_level = ++ data->dpm_table.soc_table.dpm_levels[soft_level].value; ++ + ret = vega20_upload_dpm_min_level(hwmgr, 0xFFFFFFFF); + PP_ASSERT_WITH_CODE(!ret, + "Failed to upload boot level to highest!", +@@ -2202,6 +2208,12 @@ static int vega20_force_dpm_lowest(struct pp_hwmgr *hwmgr) + data->dpm_table.mem_table.dpm_state.soft_max_level = + data->dpm_table.mem_table.dpm_levels[soft_level].value; + ++ soft_level = vega20_find_lowest_dpm_level(&(data->dpm_table.soc_table)); ++ ++ data->dpm_table.soc_table.dpm_state.soft_min_level = ++ data->dpm_table.soc_table.dpm_state.soft_max_level = ++ data->dpm_table.soc_table.dpm_levels[soft_level].value; ++ + ret = vega20_upload_dpm_min_level(hwmgr, 0xFFFFFFFF); + PP_ASSERT_WITH_CODE(!ret, + "Failed to upload boot level to highest!", +@@ -2218,8 +2230,32 @@ static int vega20_force_dpm_lowest(struct pp_hwmgr *hwmgr) + + static int vega20_unforce_dpm_levels(struct pp_hwmgr *hwmgr) + { ++ struct vega20_hwmgr *data = ++ (struct vega20_hwmgr *)(hwmgr->backend); ++ uint32_t soft_min_level, soft_max_level; + int ret = 0; + ++ soft_min_level = vega20_find_lowest_dpm_level(&(data->dpm_table.gfx_table)); ++ soft_max_level = vega20_find_highest_dpm_level(&(data->dpm_table.gfx_table)); ++ data->dpm_table.gfx_table.dpm_state.soft_min_level = ++ data->dpm_table.gfx_table.dpm_levels[soft_min_level].value; ++ data->dpm_table.gfx_table.dpm_state.soft_max_level = ++ data->dpm_table.gfx_table.dpm_levels[soft_max_level].value; ++ ++ soft_min_level = vega20_find_lowest_dpm_level(&(data->dpm_table.mem_table)); ++ soft_max_level = vega20_find_highest_dpm_level(&(data->dpm_table.mem_table)); ++ data->dpm_table.mem_table.dpm_state.soft_min_level = ++ data->dpm_table.mem_table.dpm_levels[soft_min_level].value; ++ data->dpm_table.mem_table.dpm_state.soft_max_level = ++ data->dpm_table.mem_table.dpm_levels[soft_max_level].value; ++ ++ soft_min_level = vega20_find_lowest_dpm_level(&(data->dpm_table.soc_table)); ++ soft_max_level = vega20_find_highest_dpm_level(&(data->dpm_table.soc_table)); ++ data->dpm_table.soc_table.dpm_state.soft_min_level = ++ data->dpm_table.soc_table.dpm_levels[soft_min_level].value; ++ data->dpm_table.soc_table.dpm_state.soft_max_level = ++ data->dpm_table.soc_table.dpm_levels[soft_max_level].value; ++ + ret = vega20_upload_dpm_min_level(hwmgr, 0xFFFFFFFF); + PP_ASSERT_WITH_CODE(!ret, + "Failed to upload DPM Bootup Levels!", +@@ -2457,6 +2493,7 @@ static int vega20_dpm_force_dpm_level(struct pp_hwmgr *hwmgr, + return ret; + vega20_force_clock_level(hwmgr, PP_SCLK, 1 << sclk_mask); + vega20_force_clock_level(hwmgr, PP_MCLK, 1 << mclk_mask); ++ vega20_force_clock_level(hwmgr, PP_SOCCLK, 1 << soc_mask); + break; + + case AMD_DPM_FORCED_LEVEL_MANUAL: +-- +2.17.1 + |