diff options
Diffstat (limited to 'common/recipes-kernel/linux/linux-yocto-4.19.8/1078-drm-amd-display-dal-pplib-interface-refactor-dal-par.patch')
| -rw-r--r-- | common/recipes-kernel/linux/linux-yocto-4.19.8/1078-drm-amd-display-dal-pplib-interface-refactor-dal-par.patch | 113 |
1 files changed, 113 insertions, 0 deletions
diff --git a/common/recipes-kernel/linux/linux-yocto-4.19.8/1078-drm-amd-display-dal-pplib-interface-refactor-dal-par.patch b/common/recipes-kernel/linux/linux-yocto-4.19.8/1078-drm-amd-display-dal-pplib-interface-refactor-dal-par.patch new file mode 100644 index 00000000..dbf05b06 --- /dev/null +++ b/common/recipes-kernel/linux/linux-yocto-4.19.8/1078-drm-amd-display-dal-pplib-interface-refactor-dal-par.patch @@ -0,0 +1,113 @@ +From c083d4c085c9dd9cd4ecbbcc3c47b8189fc090dc Mon Sep 17 00:00:00 2001 +From: hersen wu <hersenxs.wu@amd.com> +Date: Wed, 28 Nov 2018 16:57:56 -0500 +Subject: [PATCH 1078/2940] drm/amd/display: dal-pplib interface refactor dal + part + +[WHY] clarify dal input parameters to pplib interface, remove +un-used parameters. dal knows exactly which parameters needed +and their effects at pplib and smu sides. + +current dal sequence for dcn1_update_clock to pplib: + +1.smu10_display_clock_voltage_request for dcefclk +2.smu10_display_clock_voltage_request for fclk +3.phm_store_dal_configuration_data { + set_min_deep_sleep_dcfclk + set_active_display_count + store_cc6_data --- this data never be referenced + +new sequence will be: + +1. set_display_count --- need add new pplib interface +2. set_min_deep_sleep_dcfclk -- new pplib interface +3. set_hard_min_dcfclk_by_freq +4. set_hard_min_fclk_by_freq + +after this code refactor, smu10_display_clock_voltage_request, +phm_store_dal_configuration_data will not be needed for rv. + +Signed-off-by: hersen wu <hersenxs.wu@amd.com> +Reviewed-by: Harry Wentland <Harry.Wentland@amd.com> +Acked-by: Leo Li <sunpeng.li@amd.com> +Signed-off-by: Alex Deucher <alexander.deucher@amd.com> +--- + .../amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c | 57 +++++++++++++++++++ + 1 file changed, 57 insertions(+) + +diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c +index 1afdff967f32..9094288581dc 100644 +--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c ++++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c +@@ -559,6 +559,58 @@ void pp_rv_set_pme_wa_enable(struct pp_smu *pp) + pp_funcs->notify_smu_enable_pwe(pp_handle); + } + ++void pp_rv_set_active_display_count(struct pp_smu *pp, int count) ++{ ++ const struct dc_context *ctx = pp->dm; ++ struct amdgpu_device *adev = ctx->driver_context; ++ void *pp_handle = adev->powerplay.pp_handle; ++ const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; ++ ++ if (!pp_funcs || !pp_funcs->set_active_display_count) ++ return; ++ ++ pp_funcs->set_active_display_count(pp_handle, count); ++} ++ ++void pp_rv_set_min_deep_sleep_dcfclk(struct pp_smu *pp, int clock) ++{ ++ const struct dc_context *ctx = pp->dm; ++ struct amdgpu_device *adev = ctx->driver_context; ++ void *pp_handle = adev->powerplay.pp_handle; ++ const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; ++ ++ if (!pp_funcs || !pp_funcs->set_min_deep_sleep_dcefclk) ++ return; ++ ++ pp_funcs->set_min_deep_sleep_dcefclk(pp_handle, clock); ++} ++ ++void pp_rv_set_hard_min_dcefclk_by_freq(struct pp_smu *pp, int clock) ++{ ++ const struct dc_context *ctx = pp->dm; ++ struct amdgpu_device *adev = ctx->driver_context; ++ void *pp_handle = adev->powerplay.pp_handle; ++ const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; ++ ++ if (!pp_funcs || !pp_funcs->set_hard_min_dcefclk_by_freq) ++ return; ++ ++ pp_funcs->set_hard_min_dcefclk_by_freq(pp_handle, clock); ++} ++ ++void pp_rv_set_hard_min_fclk_by_freq(struct pp_smu *pp, int mhz) ++{ ++ const struct dc_context *ctx = pp->dm; ++ struct amdgpu_device *adev = ctx->driver_context; ++ void *pp_handle = adev->powerplay.pp_handle; ++ const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; ++ ++ if (!pp_funcs || !pp_funcs->set_hard_min_fclk_by_freq) ++ return; ++ ++ pp_funcs->set_hard_min_fclk_by_freq(pp_handle, mhz); ++} ++ + void dm_pp_get_funcs_rv( + struct dc_context *ctx, + struct pp_smu_funcs_rv *funcs) +@@ -567,4 +619,9 @@ void dm_pp_get_funcs_rv( + funcs->set_display_requirement = pp_rv_set_display_requirement; + funcs->set_wm_ranges = pp_rv_set_wm_ranges; + funcs->set_pme_wa_enable = pp_rv_set_pme_wa_enable; ++ funcs->set_display_count = pp_rv_set_active_display_count; ++ funcs->set_min_deep_sleep_dcfclk = pp_rv_set_min_deep_sleep_dcfclk; ++ funcs->set_hard_min_dcfclk_by_freq = pp_rv_set_hard_min_dcefclk_by_freq; ++ funcs->set_hard_min_fclk_by_freq = pp_rv_set_hard_min_fclk_by_freq; + } ++ +-- +2.17.1 + |