diff options
Diffstat (limited to 'common/recipes-kernel/linux/linux-yocto-4.19.8/1024-drm-amd-display-Start-using-the-new-pp_smu-interface.patch')
| -rw-r--r-- | common/recipes-kernel/linux/linux-yocto-4.19.8/1024-drm-amd-display-Start-using-the-new-pp_smu-interface.patch | 194 |
1 files changed, 194 insertions, 0 deletions
diff --git a/common/recipes-kernel/linux/linux-yocto-4.19.8/1024-drm-amd-display-Start-using-the-new-pp_smu-interface.patch b/common/recipes-kernel/linux/linux-yocto-4.19.8/1024-drm-amd-display-Start-using-the-new-pp_smu-interface.patch new file mode 100644 index 00000000..be2e6617 --- /dev/null +++ b/common/recipes-kernel/linux/linux-yocto-4.19.8/1024-drm-amd-display-Start-using-the-new-pp_smu-interface.patch @@ -0,0 +1,194 @@ +From 737dda3cae5f657cdaebae2843712e9efcc3df99 Mon Sep 17 00:00:00 2001 +From: Fatemeh Darbehani <fatemeh.darbehani@amd.com> +Date: Fri, 30 Nov 2018 15:55:01 -0500 +Subject: [PATCH 1024/2940] drm/amd/display: Start using the new pp_smu + interface + +[Why] +PPLib has impelemented the new pp_smu interface + +[How] +Use the new functions if available instead of the old interface +'set_display_requirement' and 'dcn1_pplib_apply_display_requirements'. + +Signed-off-by: Fatemeh Darbehani <fatemeh.darbehani@amd.com> +Reviewed-by: Fatemeh Darbehani <Fatemeh.Darbehani@amd.com> +Acked-by: Leo Li <sunpeng.li@amd.com> +Acked-by: Su Chung <Su.Chung@amd.com> +Signed-off-by: Alex Deucher <alexander.deucher@amd.com> +Signed-off-by: Chaudhary Amit Kumar <Chaudharyamit.Kumar@amd.com> +--- + .../amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c | 4 +- + .../drm/amd/display/dc/dcn10/dcn10_clk_mgr.c | 82 ++++++------------- + drivers/gpu/drm/amd/display/dc/dm_pp_smu.h | 4 +- + 3 files changed, 31 insertions(+), 59 deletions(-) + +diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c +index 12001a006b2d..1afdff967f32 100644 +--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c ++++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c +@@ -485,11 +485,11 @@ void pp_rv_set_display_requirement(struct pp_smu *pp, + return; + + clock.clock_type = amd_pp_dcf_clock; +- clock.clock_freq_in_khz = req->hard_min_dcefclk_khz; ++ clock.clock_freq_in_khz = req->hard_min_dcefclk_mhz; + pp_funcs->display_clock_voltage_request(pp_handle, &clock); + + clock.clock_type = amd_pp_f_clock; +- clock.clock_freq_in_khz = req->hard_min_fclk_khz; ++ clock.clock_freq_in_khz = req->hard_min_fclk_mhz; + pp_funcs->display_clock_voltage_request(pp_handle, &clock); + } + +diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_clk_mgr.c +index d4824a1b327b..9c3b87c9ede9 100644 +--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_clk_mgr.c ++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_clk_mgr.c +@@ -161,40 +161,6 @@ static int get_active_display_cnt( + return display_count; + } + +-static void notify_deep_sleep_dcfclk_to_smu( +- struct pp_smu_funcs_rv *pp_smu, int min_dcef_deep_sleep_clk_khz) +-{ +- int min_dcef_deep_sleep_clk_mhz; //minimum required DCEF Deep Sleep clock in mhz +- /* +- * if function pointer not set up, this message is +- * sent as part of pplib_apply_display_requirements. +- * So just return. +- */ +- if (!pp_smu || !pp_smu->set_min_deep_sleep_dcfclk) +- return; +- +- min_dcef_deep_sleep_clk_mhz = (min_dcef_deep_sleep_clk_khz + 999) / 1000; //Round up +- pp_smu->set_min_deep_sleep_dcfclk(&pp_smu->pp_smu, min_dcef_deep_sleep_clk_mhz); +-} +- +-static void notify_hard_min_dcfclk_to_smu( +- struct pp_smu_funcs_rv *pp_smu, int min_dcf_clk_khz) +-{ +- int min_dcf_clk_mhz; //minimum required DCF clock in mhz +- +- /* +- * if function pointer not set up, this message is +- * sent as part of pplib_apply_display_requirements. +- * So just return. +- */ +- if (!pp_smu || !pp_smu->set_hard_min_dcfclk_by_freq) +- return; +- +- min_dcf_clk_mhz = min_dcf_clk_khz / 1000; +- +- pp_smu->set_hard_min_dcfclk_by_freq(&pp_smu->pp_smu, min_dcf_clk_mhz); +-} +- + static void dcn1_update_clocks(struct clk_mgr *clk_mgr, + struct dc_state *context, + bool safe_to_lower) +@@ -206,7 +172,6 @@ static void dcn1_update_clocks(struct clk_mgr *clk_mgr, + &dc->res_pool->pp_smu_req; + struct pp_smu_display_requirement_rv smu_req = *smu_req_cur; + struct pp_smu_funcs_rv *pp_smu = dc->res_pool->pp_smu; +- uint32_t requested_dcf_clock_in_khz = 0; + bool send_request_to_increase = false; + bool send_request_to_lower = false; + int display_count; +@@ -226,8 +191,8 @@ static void dcn1_update_clocks(struct clk_mgr *clk_mgr, + */ + if (pp_smu->set_display_count) + pp_smu->set_display_count(&pp_smu->pp_smu, display_count); +- else +- smu_req.display_count = display_count; ++ ++ smu_req.display_count = display_count; + + } + +@@ -265,7 +230,7 @@ static void dcn1_update_clocks(struct clk_mgr *clk_mgr, + if (should_set_clock(safe_to_lower, + new_clocks->dcfclk_deep_sleep_khz, clk_mgr->clks.dcfclk_deep_sleep_khz)) { + clk_mgr->clks.dcfclk_deep_sleep_khz = new_clocks->dcfclk_deep_sleep_khz; +- smu_req.min_deep_sleep_dcefclk_mhz = new_clocks->dcfclk_deep_sleep_khz; ++ smu_req.min_deep_sleep_dcefclk_mhz = (new_clocks->dcfclk_deep_sleep_khz + 999) / 1000; + + send_request_to_lower = true; + } +@@ -275,15 +240,18 @@ static void dcn1_update_clocks(struct clk_mgr *clk_mgr, + */ + if (send_request_to_increase) { + /*use dcfclk to request voltage*/ +- requested_dcf_clock_in_khz = dcn_find_dcfclk_suits_all(dc, new_clocks); +- +- notify_hard_min_dcfclk_to_smu(pp_smu, requested_dcf_clock_in_khz); +- +- if (pp_smu->set_display_requirement) +- pp_smu->set_display_requirement(&pp_smu->pp_smu, &smu_req); +- +- notify_deep_sleep_dcfclk_to_smu(pp_smu, clk_mgr->clks.dcfclk_deep_sleep_khz); +- dcn1_pplib_apply_display_requirements(dc, context); ++ if (pp_smu->set_hard_min_fclk_by_freq && ++ pp_smu->set_hard_min_dcfclk_by_freq && ++ pp_smu->set_min_deep_sleep_dcfclk) { ++ ++ pp_smu->set_hard_min_fclk_by_freq(&pp_smu->pp_smu, smu_req.hard_min_fclk_mhz); ++ pp_smu->set_hard_min_dcfclk_by_freq(&pp_smu->pp_smu, smu_req.hard_min_dcefclk_mhz); ++ pp_smu->set_min_deep_sleep_dcfclk(&pp_smu->pp_smu, smu_req.min_deep_sleep_dcefclk_mhz); ++ } else { ++ if (pp_smu->set_display_requirement) ++ pp_smu->set_display_requirement(&pp_smu->pp_smu, &smu_req); ++ dcn1_pplib_apply_display_requirements(dc, context); ++ } + } + + /* dcn1 dppclk is tied to dispclk */ +@@ -298,15 +266,19 @@ static void dcn1_update_clocks(struct clk_mgr *clk_mgr, + + if (!send_request_to_increase && send_request_to_lower) { + /*use dcfclk to request voltage*/ +- requested_dcf_clock_in_khz = dcn_find_dcfclk_suits_all(dc, new_clocks); +- +- notify_hard_min_dcfclk_to_smu(pp_smu, requested_dcf_clock_in_khz); +- +- if (pp_smu->set_display_requirement) +- pp_smu->set_display_requirement(&pp_smu->pp_smu, &smu_req); ++ if (pp_smu->set_hard_min_fclk_by_freq && ++ pp_smu->set_hard_min_dcfclk_by_freq && ++ pp_smu->set_min_deep_sleep_dcfclk) { ++ ++ pp_smu->set_hard_min_fclk_by_freq(&pp_smu->pp_smu, smu_req.hard_min_fclk_mhz); ++ pp_smu->set_hard_min_dcfclk_by_freq(&pp_smu->pp_smu, smu_req.hard_min_dcefclk_mhz); ++ pp_smu->set_min_deep_sleep_dcfclk(&pp_smu->pp_smu, smu_req.min_deep_sleep_dcefclk_mhz); ++ } else { ++ if (pp_smu->set_display_requirement) ++ pp_smu->set_display_requirement(&pp_smu->pp_smu, &smu_req); ++ dcn1_pplib_apply_display_requirements(dc, context); ++ } + +- notify_deep_sleep_dcfclk_to_smu(pp_smu, clk_mgr->clks.dcfclk_deep_sleep_khz); +- dcn1_pplib_apply_display_requirements(dc, context); + } + + +diff --git a/drivers/gpu/drm/amd/display/dc/dm_pp_smu.h b/drivers/gpu/drm/amd/display/dc/dm_pp_smu.h +index b10272d6b84b..90e94b030113 100644 +--- a/drivers/gpu/drm/amd/display/dc/dm_pp_smu.h ++++ b/drivers/gpu/drm/amd/display/dc/dm_pp_smu.h +@@ -81,12 +81,12 @@ struct pp_smu_display_requirement_rv { + /* PPSMC_MSG_SetHardMinFclkByFreq: khz + * FCLK will vary with DPM, but never below requested hard min + */ +- unsigned int hard_min_fclk_khz; ++ unsigned int hard_min_fclk_mhz; + + /* PPSMC_MSG_SetHardMinDcefclkByFreq: khz + * fixed clock at requested freq, either from FCH bypass or DFS + */ +- unsigned int hard_min_dcefclk_khz; ++ unsigned int hard_min_dcefclk_mhz; + + /* PPSMC_MSG_SetMinDeepSleepDcefclk: mhz + * when DF is in cstate, dcf clock is further divided down +-- +2.17.1 + |