diff options
Diffstat (limited to 'common/recipes-kernel/linux/linux-yocto-4.19.8/1002-drm-amd-display-Add-pixel-clock-values-to-dtn-logs.patch')
| -rw-r--r-- | common/recipes-kernel/linux/linux-yocto-4.19.8/1002-drm-amd-display-Add-pixel-clock-values-to-dtn-logs.patch | 61 |
1 files changed, 61 insertions, 0 deletions
diff --git a/common/recipes-kernel/linux/linux-yocto-4.19.8/1002-drm-amd-display-Add-pixel-clock-values-to-dtn-logs.patch b/common/recipes-kernel/linux/linux-yocto-4.19.8/1002-drm-amd-display-Add-pixel-clock-values-to-dtn-logs.patch new file mode 100644 index 00000000..7efbc436 --- /dev/null +++ b/common/recipes-kernel/linux/linux-yocto-4.19.8/1002-drm-amd-display-Add-pixel-clock-values-to-dtn-logs.patch @@ -0,0 +1,61 @@ +From 52d30c3a12078b3666115c0ead4f86e3604d8d20 Mon Sep 17 00:00:00 2001 +From: Fatemeh Darbehani <fatemeh.darbehani@amd.com> +Date: Mon, 19 Nov 2018 13:23:21 -0500 +Subject: [PATCH 1002/2940] drm/amd/display: Add pixel clock values to dtn logs + +[Why] +To make sure future changes in DAL for SMU msgs will not change the current behaviour +and to make sure clock registeres are programmed correctly based on SMU msgs +that DAL sends. + +Signed-off-by: Fatemeh Darbehani <fatemeh.darbehani@amd.com> +Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> +Acked-by: Leo Li <sunpeng.li@amd.com> +Acked-by: Yongqiang Sun <yongqiang.sun@amd.com> +Signed-off-by: Alex Deucher <alexander.deucher@amd.com> +--- + .../drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c | 9 ++++++--- + 1 file changed, 6 insertions(+), 3 deletions(-) + +diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c +index 82175820b0cf..ae4fd5ec9f74 100644 +--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c ++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c +@@ -419,20 +419,22 @@ static unsigned int dcn10_get_otg_states(struct dc *dc, char *pBuf, unsigned int + unsigned int remaining_buffer = bufSize; + + chars_printed = snprintf_count(pBuf, remaining_buffer, "instance,v_bs,v_be,v_ss,v_se,vpol,vmax,vmin,vmax_sel,vmin_sel," +- "h_bs,h_be,h_ss,h_se,hpol,htot,vtot,underflow\n"); ++ "h_bs,h_be,h_ss,h_se,hpol,htot,vtot,underflow,pixelclk[khz]\n"); + remaining_buffer -= chars_printed; + pBuf += chars_printed; + + for (i = 0; i < pool->timing_generator_count; i++) { + struct timing_generator *tg = pool->timing_generators[i]; + struct dcn_otg_state s = {0}; ++ int pix_clk = 0; + + optc1_read_otg_state(DCN10TG_FROM_TG(tg), &s); ++ pix_clk = dc->current_state->res_ctx.pipe_ctx[i].stream_res.pix_clk_params.requested_pix_clk; + + //only print if OTG master is enabled + if (s.otg_enabled & 1) { + chars_printed = snprintf_count(pBuf, remaining_buffer, "%x,%d,%d,%d,%d,%d,%d,%d,%d,%d," +- "%d,%d,%d,%d,%d,%d,%d,%d" ++ "%d,%d,%d,%d,%d,%d,%d,%d,%d" + "\n", + tg->inst, + s.v_blank_start, +@@ -451,7 +453,8 @@ static unsigned int dcn10_get_otg_states(struct dc *dc, char *pBuf, unsigned int + s.h_sync_a_pol, + s.h_total, + s.v_total, +- s.underflow_occurred_status); ++ s.underflow_occurred_status, ++ pix_clk); + + remaining_buffer -= chars_printed; + pBuf += chars_printed; +-- +2.17.1 + |