diff options
Diffstat (limited to 'common/recipes-kernel/linux/linux-yocto-4.19.8/0970-drm-amdgpu-nbio7.4-add-hw-bug-workaround-for-vega20.patch')
-rw-r--r-- | common/recipes-kernel/linux/linux-yocto-4.19.8/0970-drm-amdgpu-nbio7.4-add-hw-bug-workaround-for-vega20.patch | 45 |
1 files changed, 45 insertions, 0 deletions
diff --git a/common/recipes-kernel/linux/linux-yocto-4.19.8/0970-drm-amdgpu-nbio7.4-add-hw-bug-workaround-for-vega20.patch b/common/recipes-kernel/linux/linux-yocto-4.19.8/0970-drm-amdgpu-nbio7.4-add-hw-bug-workaround-for-vega20.patch new file mode 100644 index 00000000..3dcd0432 --- /dev/null +++ b/common/recipes-kernel/linux/linux-yocto-4.19.8/0970-drm-amdgpu-nbio7.4-add-hw-bug-workaround-for-vega20.patch @@ -0,0 +1,45 @@ +From 368094af54681f795fe16224dc49ec6b39955296 Mon Sep 17 00:00:00 2001 +From: Alex Deucher <alexander.deucher@amd.com> +Date: Wed, 19 Dec 2018 18:05:41 -0500 +Subject: [PATCH 0970/2940] drm/amdgpu/nbio7.4: add hw bug workaround for + vega20 + +Configure PCIE_CI_CNTL to work around a hw bug that affects +some multi-GPU compute workloads. + +Acked-by: Feifei Xu <Feifei.Xu@amd.com> +Reviewed-by: Harish Kasiviswanathan <Harish.Kasiviswanathan@amd.com> +Signed-off-by: Alex Deucher <alexander.deucher@amd.com> +--- + drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c | 7 +++++++ + 1 file changed, 7 insertions(+) + +diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c b/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c +index f8cee95d61cc..4cd31a276dcd 100644 +--- a/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c ++++ b/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c +@@ -31,6 +31,7 @@ + + #define smnCPM_CONTROL 0x11180460 + #define smnPCIE_CNTL2 0x11180070 ++#define smnPCIE_CI_CNTL 0x11180080 + + static u32 nbio_v7_4_get_rev_id(struct amdgpu_device *adev) + { +@@ -222,7 +223,13 @@ static void nbio_v7_4_detect_hw_virt(struct amdgpu_device *adev) + + static void nbio_v7_4_init_registers(struct amdgpu_device *adev) + { ++ uint32_t def, data; ++ ++ def = data = RREG32_PCIE(smnPCIE_CI_CNTL); ++ data = REG_SET_FIELD(data, PCIE_CI_CNTL, CI_SLV_ORDERING_DIS, 1); + ++ if (def != data) ++ WREG32_PCIE(smnPCIE_CI_CNTL, data); + } + + const struct amdgpu_nbio_funcs nbio_v7_4_funcs = { +-- +2.17.1 + |