diff options
Diffstat (limited to 'common/recipes-kernel/linux/linux-yocto-4.19.8/0969-drm-amdgpu-nbio6.1-add-hw-bug-workaround-for-vega10-.patch')
-rw-r--r-- | common/recipes-kernel/linux/linux-yocto-4.19.8/0969-drm-amdgpu-nbio6.1-add-hw-bug-workaround-for-vega10-.patch | 44 |
1 files changed, 44 insertions, 0 deletions
diff --git a/common/recipes-kernel/linux/linux-yocto-4.19.8/0969-drm-amdgpu-nbio6.1-add-hw-bug-workaround-for-vega10-.patch b/common/recipes-kernel/linux/linux-yocto-4.19.8/0969-drm-amdgpu-nbio6.1-add-hw-bug-workaround-for-vega10-.patch new file mode 100644 index 00000000..383f334b --- /dev/null +++ b/common/recipes-kernel/linux/linux-yocto-4.19.8/0969-drm-amdgpu-nbio6.1-add-hw-bug-workaround-for-vega10-.patch @@ -0,0 +1,44 @@ +From 462b93f189d6b96634c8f20b87b5abe629241535 Mon Sep 17 00:00:00 2001 +From: Alex Deucher <alexander.deucher@amd.com> +Date: Wed, 19 Dec 2018 18:01:53 -0500 +Subject: [PATCH 0969/2940] drm/amdgpu/nbio6.1: add hw bug workaround for + vega10/12 + +Configure PCIE_CI_CNTL to work around a hw bug that affects +some multi-GPU compute workloads. + +Acked-by: Feifei Xu <Feifei.Xu@amd.com> +Reviewed-by: Harish Kasiviswanathan <Harish.Kasiviswanathan@amd.com> +Signed-off-by: Alex Deucher <alexander.deucher@amd.com> +--- + drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c | 7 +++++++ + 1 file changed, 7 insertions(+) + +diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c b/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c +index 6f9c54978cc1..accdedd63c98 100644 +--- a/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c ++++ b/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c +@@ -32,6 +32,7 @@ + #define smnCPM_CONTROL 0x11180460 + #define smnPCIE_CNTL2 0x11180070 + #define smnPCIE_CONFIG_CNTL 0x11180044 ++#define smnPCIE_CI_CNTL 0x11180080 + + static u32 nbio_v6_1_get_rev_id(struct amdgpu_device *adev) + { +@@ -270,6 +271,12 @@ static void nbio_v6_1_init_registers(struct amdgpu_device *adev) + + if (def != data) + WREG32_PCIE(smnPCIE_CONFIG_CNTL, data); ++ ++ def = data = RREG32_PCIE(smnPCIE_CI_CNTL); ++ data = REG_SET_FIELD(data, PCIE_CI_CNTL, CI_SLV_ORDERING_DIS, 1); ++ ++ if (def != data) ++ WREG32_PCIE(smnPCIE_CI_CNTL, data); + } + + const struct amdgpu_nbio_funcs nbio_v6_1_funcs = { +-- +2.17.1 + |