diff options
Diffstat (limited to 'common/recipes-kernel/linux/linux-yocto-4.19.8/0852-drm-amdgpu-Add-delay-after-enable-RLC-ucode.patch')
| -rw-r--r-- | common/recipes-kernel/linux/linux-yocto-4.19.8/0852-drm-amdgpu-Add-delay-after-enable-RLC-ucode.patch | 46 |
1 files changed, 46 insertions, 0 deletions
diff --git a/common/recipes-kernel/linux/linux-yocto-4.19.8/0852-drm-amdgpu-Add-delay-after-enable-RLC-ucode.patch b/common/recipes-kernel/linux/linux-yocto-4.19.8/0852-drm-amdgpu-Add-delay-after-enable-RLC-ucode.patch new file mode 100644 index 00000000..c050e36f --- /dev/null +++ b/common/recipes-kernel/linux/linux-yocto-4.19.8/0852-drm-amdgpu-Add-delay-after-enable-RLC-ucode.patch @@ -0,0 +1,46 @@ +From e691f79a9ba0045eaef9d155470bd492b3047af7 Mon Sep 17 00:00:00 2001 +From: shaoyunl <shaoyun.liu@amd.com> +Date: Thu, 22 Nov 2018 11:45:24 -0500 +Subject: [PATCH 0852/2940] drm/amdgpu: Add delay after enable RLC ucode + +Driver shouldn't try to access any GFX registers until RLC is idle. +During the test, it took 12 seconds for RLC to clear the BUSY bit +in RLC_GPM_STAT register which is un-acceptable for driver. +As per RLC engineer, it would take RLC Ucode less than 10,000 GFXCLK +cycles to finish its critical section. In a lowest 300M enginer clock +setting(default from vbios), 50 us delay is enough. + +This commit fix the hang when RLC introduce the work around for XGMI +which requires more cycles to setup more registers than normal + +Signed-off-by: shaoyunl <shaoyun.liu@amd.com> +Acked-by: Felix Kuehling <Felix.Kuehling@amd.com> +Signed-off-by: Alex Deucher <alexander.deucher@amd.com> +--- + drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 7 ++++--- + 1 file changed, 4 insertions(+), 3 deletions(-) + +diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c +index e6600acd481d..269c1ef9421d 100644 +--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c ++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c +@@ -2344,12 +2344,13 @@ static void gfx_v9_0_rlc_start(struct amdgpu_device *adev) + #endif + + WREG32_FIELD15(GC, 0, RLC_CNTL, RLC_ENABLE_F32, 1); ++ udelay(50); + + /* carrizo do enable cp interrupt after cp inited */ +- if (!(adev->flags & AMD_IS_APU)) ++ if (!(adev->flags & AMD_IS_APU)) { + gfx_v9_0_enable_gui_idle_interrupt(adev, true); +- +- udelay(50); ++ udelay(50); ++ } + + #ifdef AMDGPU_RLC_DEBUG_RETRY + /* RLC_GPM_GENERAL_6 : RLC Ucode version */ +-- +2.17.1 + |