diff options
Diffstat (limited to 'common/recipes-kernel/linux/linux-yocto-4.19.8/0829-drm-amdgpu-Enable-HDP-memory-light-sleep.patch')
| -rw-r--r-- | common/recipes-kernel/linux/linux-yocto-4.19.8/0829-drm-amdgpu-Enable-HDP-memory-light-sleep.patch | 78 |
1 files changed, 78 insertions, 0 deletions
diff --git a/common/recipes-kernel/linux/linux-yocto-4.19.8/0829-drm-amdgpu-Enable-HDP-memory-light-sleep.patch b/common/recipes-kernel/linux/linux-yocto-4.19.8/0829-drm-amdgpu-Enable-HDP-memory-light-sleep.patch new file mode 100644 index 00000000..8bbfbafa --- /dev/null +++ b/common/recipes-kernel/linux/linux-yocto-4.19.8/0829-drm-amdgpu-Enable-HDP-memory-light-sleep.patch @@ -0,0 +1,78 @@ +From 3c125cc1222ea0190d3d3b986c508b0ffb9ee687 Mon Sep 17 00:00:00 2001 +From: Kenneth Feng <kenneth.feng@amd.com> +Date: Mon, 19 Nov 2018 14:49:16 +0800 +Subject: [PATCH 0829/2940] drm/amdgpu: Enable HDP memory light sleep + +Due to the register name and setting change of HDP +memory light sleep on Vega20,change accordingly in +the driver. + +Signed-off-by: Kenneth Feng <kenneth.feng@amd.com> +Reviewed-by: Evan Quan <evan.quan@amd.com> +Signed-off-by: Alex Deucher <alexander.deucher@amd.com> +--- + drivers/gpu/drm/amd/amdgpu/soc15.c | 39 ++++++++++++++++++++++++------ + 1 file changed, 32 insertions(+), 7 deletions(-) + +diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c +index c4edd9ac0599..a8ec261ab250 100644 +--- a/drivers/gpu/drm/amd/amdgpu/soc15.c ++++ b/drivers/gpu/drm/amd/amdgpu/soc15.c +@@ -65,6 +65,13 @@ + #define mmMP0_MISC_LIGHT_SLEEP_CTRL 0x01ba + #define mmMP0_MISC_LIGHT_SLEEP_CTRL_BASE_IDX 0 + ++/* for Vega20 register name change */ ++#define mmHDP_MEM_POWER_CTRL 0x00d4 ++#define HDP_MEM_POWER_CTRL__IPH_MEM_POWER_CTRL_EN_MASK 0x00000001L ++#define HDP_MEM_POWER_CTRL__IPH_MEM_POWER_LS_EN_MASK 0x00000002L ++#define HDP_MEM_POWER_CTRL__RC_MEM_POWER_CTRL_EN_MASK 0x00010000L ++#define HDP_MEM_POWER_CTRL__RC_MEM_POWER_LS_EN_MASK 0x00020000L ++#define mmHDP_MEM_POWER_CTRL_BASE_IDX 0 + /* + * Indirect registers accessor + */ +@@ -869,15 +876,33 @@ static void soc15_update_hdp_light_sleep(struct amdgpu_device *adev, bool enable + { + uint32_t def, data; + +- def = data = RREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_LS)); ++ if (adev->asic_type == CHIP_VEGA20) { ++ def = data = RREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_CTRL)); + +- if (enable && (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS)) +- data |= HDP_MEM_POWER_LS__LS_ENABLE_MASK; +- else +- data &= ~HDP_MEM_POWER_LS__LS_ENABLE_MASK; ++ if (enable && (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS)) ++ data |= HDP_MEM_POWER_CTRL__IPH_MEM_POWER_CTRL_EN_MASK | ++ HDP_MEM_POWER_CTRL__IPH_MEM_POWER_LS_EN_MASK | ++ HDP_MEM_POWER_CTRL__RC_MEM_POWER_CTRL_EN_MASK | ++ HDP_MEM_POWER_CTRL__RC_MEM_POWER_LS_EN_MASK; ++ else ++ data &= ~(HDP_MEM_POWER_CTRL__IPH_MEM_POWER_CTRL_EN_MASK | ++ HDP_MEM_POWER_CTRL__IPH_MEM_POWER_LS_EN_MASK | ++ HDP_MEM_POWER_CTRL__RC_MEM_POWER_CTRL_EN_MASK | ++ HDP_MEM_POWER_CTRL__RC_MEM_POWER_LS_EN_MASK); + +- if (def != data) +- WREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_LS), data); ++ if (def != data) ++ WREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_CTRL), data); ++ } else { ++ def = data = RREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_LS)); ++ ++ if (enable && (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS)) ++ data |= HDP_MEM_POWER_LS__LS_ENABLE_MASK; ++ else ++ data &= ~HDP_MEM_POWER_LS__LS_ENABLE_MASK; ++ ++ if (def != data) ++ WREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_LS), data); ++ } + } + + static void soc15_update_drm_clock_gating(struct amdgpu_device *adev, bool enable) +-- +2.17.1 + |