diff options
Diffstat (limited to 'common/recipes-kernel/linux/linux-yocto-4.19.8/0664-drm-amd-pp-Fix-pp_sclk-mclk_od-not-work-on-Vega10.patch')
| -rw-r--r-- | common/recipes-kernel/linux/linux-yocto-4.19.8/0664-drm-amd-pp-Fix-pp_sclk-mclk_od-not-work-on-Vega10.patch | 59 |
1 files changed, 59 insertions, 0 deletions
diff --git a/common/recipes-kernel/linux/linux-yocto-4.19.8/0664-drm-amd-pp-Fix-pp_sclk-mclk_od-not-work-on-Vega10.patch b/common/recipes-kernel/linux/linux-yocto-4.19.8/0664-drm-amd-pp-Fix-pp_sclk-mclk_od-not-work-on-Vega10.patch new file mode 100644 index 00000000..f95e6dc9 --- /dev/null +++ b/common/recipes-kernel/linux/linux-yocto-4.19.8/0664-drm-amd-pp-Fix-pp_sclk-mclk_od-not-work-on-Vega10.patch @@ -0,0 +1,59 @@ +From 20053b3fbf3e42061579b202e6f474c32f5ed170 Mon Sep 17 00:00:00 2001 +From: Rex Zhu <Rex.Zhu@amd.com> +Date: Tue, 30 Oct 2018 20:01:59 +0800 +Subject: [PATCH 0664/2940] drm/amd/pp: Fix pp_sclk/mclk_od not work on Vega10 + +not update dpm table with user's setting. + +Reviewed-by: Alex Deucher <alexander.deucher@amd.com> +Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> +Signed-off-by: Alex Deucher <alexander.deucher@amd.com> +--- + .../drm/amd/powerplay/hwmgr/vega10_hwmgr.c | 31 +++++++++++++++++++ + 1 file changed, 31 insertions(+) + +diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c +index 419a1d77d661..3fd68df23932 100644 +--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c ++++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c +@@ -3249,6 +3249,37 @@ static int vega10_apply_state_adjust_rules(struct pp_hwmgr *hwmgr, + static int vega10_find_dpm_states_clocks_in_dpm_table(struct pp_hwmgr *hwmgr, const void *input) + { + struct vega10_hwmgr *data = hwmgr->backend; ++ const struct phm_set_power_state_input *states = ++ (const struct phm_set_power_state_input *)input; ++ const struct vega10_power_state *vega10_ps = ++ cast_const_phw_vega10_power_state(states->pnew_state); ++ struct vega10_single_dpm_table *sclk_table = &(data->dpm_table.gfx_table); ++ uint32_t sclk = vega10_ps->performance_levels ++ [vega10_ps->performance_level_count - 1].gfx_clock; ++ struct vega10_single_dpm_table *mclk_table = &(data->dpm_table.mem_table); ++ uint32_t mclk = vega10_ps->performance_levels ++ [vega10_ps->performance_level_count - 1].mem_clock; ++ uint32_t i; ++ ++ for (i = 0; i < sclk_table->count; i++) { ++ if (sclk == sclk_table->dpm_levels[i].value) ++ break; ++ } ++ ++ if (i >= sclk_table->count) { ++ data->need_update_dpm_table |= DPMTABLE_OD_UPDATE_SCLK; ++ sclk_table->dpm_levels[i-1].value = sclk; ++ } ++ ++ for (i = 0; i < mclk_table->count; i++) { ++ if (mclk == mclk_table->dpm_levels[i].value) ++ break; ++ } ++ ++ if (i >= mclk_table->count) { ++ data->need_update_dpm_table |= DPMTABLE_OD_UPDATE_MCLK; ++ mclk_table->dpm_levels[i-1].value = mclk; ++ } + + if (data->display_timing.num_existing_displays != hwmgr->display_config->num_display) + data->need_update_dpm_table |= DPMTABLE_UPDATE_MCLK; +-- +2.17.1 + |