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Diffstat (limited to 'common/recipes-kernel/linux/linux-yocto-4.19.8/0601-drm-amd-display-Raise-dispclk-value-for-CZ.patch')
-rw-r--r--common/recipes-kernel/linux/linux-yocto-4.19.8/0601-drm-amd-display-Raise-dispclk-value-for-CZ.patch48
1 files changed, 48 insertions, 0 deletions
diff --git a/common/recipes-kernel/linux/linux-yocto-4.19.8/0601-drm-amd-display-Raise-dispclk-value-for-CZ.patch b/common/recipes-kernel/linux/linux-yocto-4.19.8/0601-drm-amd-display-Raise-dispclk-value-for-CZ.patch
new file mode 100644
index 00000000..e8248d8d
--- /dev/null
+++ b/common/recipes-kernel/linux/linux-yocto-4.19.8/0601-drm-amd-display-Raise-dispclk-value-for-CZ.patch
@@ -0,0 +1,48 @@
+From 70449341d927d1b44bce734e715b853119efbd12 Mon Sep 17 00:00:00 2001
+From: Kalyan Alle <kalyan.alle@amd.com>
+Date: Tue, 20 Nov 2018 16:50:29 -0500
+Subject: [PATCH 0601/2940] drm/amd/display: Raise dispclk value for CZ.
+
+[Why]
+The visual corruption due to low display clock value.
+Observed on 4k@60Hz.
+
+[How]
+There was earlier patch for dspclk:
+'drm/amd/display: Raise dispclk value for dce_update_clocks'
+Adding +15% workaround also to to dce11_update_clocks
+
+Signed-off-by: Roman Li <Roman.Li@amd.com>
+Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com>
+Signed-off-by: Kalyan Alle <kalyan.alle@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c | 6 ++++++
+ 1 file changed, 6 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c
+index 493e2f4933aa..1dfe93ea673b 100644
+--- a/drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c
++++ b/drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c
+@@ -648,6 +648,10 @@ static void dce11_update_clocks(struct clk_mgr *clk_mgr,
+ {
+ struct dce_clk_mgr *clk_mgr_dce = TO_DCE_CLK_MGR(clk_mgr);
+ struct dm_pp_power_level_change_request level_change_req;
++ int unpatched_disp_clk = context->bw.dce.dispclk_khz;
++
++ if (!clk_mgr_dce->dfs_bypass_active)
++ context->bw.dce.dispclk_khz = context->bw.dce.dispclk_khz * 115 / 100;
+
+ level_change_req.power_level = dce_get_required_clocks_state(clk_mgr, context);
+ /* get max clock state from PPLIB */
+@@ -662,6 +666,8 @@ static void dce11_update_clocks(struct clk_mgr *clk_mgr,
+ clk_mgr->clks.dispclk_khz = context->bw.dce.dispclk_khz;
+ }
+ dce11_pplib_apply_display_requirements(clk_mgr->ctx->dc, context);
++
++ context->bw.dce.dispclk_khz = unpatched_disp_clk;
+ }
+
+ static void dce112_update_clocks(struct clk_mgr *clk_mgr,
+--
+2.17.1
+