diff options
Diffstat (limited to 'common/recipes-kernel/linux/linux-yocto-4.19.8/0557-drm-amd-powerplay-correct-the-clocks-for-DAL-to-be-K.patch')
| -rw-r--r-- | common/recipes-kernel/linux/linux-yocto-4.19.8/0557-drm-amd-powerplay-correct-the-clocks-for-DAL-to-be-K.patch | 118 |
1 files changed, 118 insertions, 0 deletions
diff --git a/common/recipes-kernel/linux/linux-yocto-4.19.8/0557-drm-amd-powerplay-correct-the-clocks-for-DAL-to-be-K.patch b/common/recipes-kernel/linux/linux-yocto-4.19.8/0557-drm-amd-powerplay-correct-the-clocks-for-DAL-to-be-K.patch new file mode 100644 index 00000000..11008598 --- /dev/null +++ b/common/recipes-kernel/linux/linux-yocto-4.19.8/0557-drm-amd-powerplay-correct-the-clocks-for-DAL-to-be-K.patch @@ -0,0 +1,118 @@ +From 2ec87d80ff624d17ef34d19654bf0e0e5c3639d8 Mon Sep 17 00:00:00 2001 +From: Evan Quan <evan.quan@amd.com> +Date: Tue, 23 Oct 2018 14:31:38 +0800 +Subject: [PATCH 0557/2940] drm/amd/powerplay: correct the clocks for DAL to be + Khz unit + +Currently the clocks reported are in 10Khz unit. Correct them +as Khz unit as DAL wanted. + +Change-Id: I91e9f4b460efbdc0ba223901b6c40e576523686d +Signed-off-by: Evan Quan <evan.quan@amd.com> +Reviewed-by: Feifei Xu<Feifei.Xu@amd.com> +Reviewed-by: Rex Zhu <Rex.Zhu@amd.com> +--- + .../drm/amd/powerplay/hwmgr/vega20_hwmgr.c | 21 +++++++++---------- + 1 file changed, 10 insertions(+), 11 deletions(-) + +diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c +index b4dbbb7c334c..810c60969496 100644 +--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c ++++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c +@@ -2012,7 +2012,6 @@ int vega20_display_clock_voltage_request(struct pp_hwmgr *hwmgr, + if (data->smu_features[GNLD_DPM_DCEFCLK].enabled) { + switch (clk_type) { + case amd_pp_dcef_clock: +- clk_freq = clock_req->clock_freq_in_khz / 100; + clk_select = PPCLK_DCEFCLK; + break; + case amd_pp_disp_clock: +@@ -2063,7 +2062,7 @@ static int vega20_notify_smc_display_config_after_ps_adjustment( + + if (data->smu_features[GNLD_DPM_DCEFCLK].supported) { + clock_req.clock_type = amd_pp_dcef_clock; +- clock_req.clock_freq_in_khz = min_clocks.dcefClock; ++ clock_req.clock_freq_in_khz = min_clocks.dcefClock * 10; + if (!vega20_display_clock_voltage_request(hwmgr, &clock_req)) { + if (data->smu_features[GNLD_DS_DCEFCLK].supported) + PP_ASSERT_WITH_CODE((ret = smum_send_msg_to_smc_with_parameter( +@@ -2353,7 +2352,7 @@ static int vega20_get_sclks(struct pp_hwmgr *hwmgr, + + for (i = 0; i < count; i++) { + clocks->data[i].clocks_in_khz = +- dpm_table->dpm_levels[i].value * 100; ++ dpm_table->dpm_levels[i].value * 1000; + clocks->data[i].latency_in_us = 0; + } + +@@ -2383,7 +2382,7 @@ static int vega20_get_memclocks(struct pp_hwmgr *hwmgr, + for (i = 0; i < count; i++) { + clocks->data[i].clocks_in_khz = + data->mclk_latency_table.entries[i].frequency = +- dpm_table->dpm_levels[i].value * 100; ++ dpm_table->dpm_levels[i].value * 1000; + clocks->data[i].latency_in_us = + data->mclk_latency_table.entries[i].latency = + vega20_get_mem_latency(hwmgr, dpm_table->dpm_levels[i].value); +@@ -2408,7 +2407,7 @@ static int vega20_get_dcefclocks(struct pp_hwmgr *hwmgr, + + for (i = 0; i < count; i++) { + clocks->data[i].clocks_in_khz = +- dpm_table->dpm_levels[i].value * 100; ++ dpm_table->dpm_levels[i].value * 1000; + clocks->data[i].latency_in_us = 0; + } + +@@ -2431,7 +2430,7 @@ static int vega20_get_socclocks(struct pp_hwmgr *hwmgr, + + for (i = 0; i < count; i++) { + clocks->data[i].clocks_in_khz = +- dpm_table->dpm_levels[i].value * 100; ++ dpm_table->dpm_levels[i].value * 1000; + clocks->data[i].latency_in_us = 0; + } + +@@ -2582,11 +2581,11 @@ static int vega20_odn_edit_dpm_table(struct pp_hwmgr *hwmgr, + return -EINVAL; + } + +- if (input_clk < clocks.data[0].clocks_in_khz / 100 || ++ if (input_clk < clocks.data[0].clocks_in_khz / 1000 || + input_clk > od8_settings[OD8_SETTING_UCLK_FMAX].max_value) { + pr_info("clock freq %d is not within allowed range [%d - %d]\n", + input_clk, +- clocks.data[0].clocks_in_khz / 100, ++ clocks.data[0].clocks_in_khz / 1000, + od8_settings[OD8_SETTING_UCLK_FMAX].max_value); + return -EINVAL; + } +@@ -2738,7 +2737,7 @@ static int vega20_print_clock_levels(struct pp_hwmgr *hwmgr, + + for (i = 0; i < clocks.num_levels; i++) + size += sprintf(buf + size, "%d: %uMhz %s\n", +- i, clocks.data[i].clocks_in_khz / 100, ++ i, clocks.data[i].clocks_in_khz / 1000, + (clocks.data[i].clocks_in_khz == now) ? "*" : ""); + break; + +@@ -2755,7 +2754,7 @@ static int vega20_print_clock_levels(struct pp_hwmgr *hwmgr, + + for (i = 0; i < clocks.num_levels; i++) + size += sprintf(buf + size, "%d: %uMhz %s\n", +- i, clocks.data[i].clocks_in_khz / 100, ++ i, clocks.data[i].clocks_in_khz / 1000, + (clocks.data[i].clocks_in_khz == now) ? "*" : ""); + break; + +@@ -2820,7 +2819,7 @@ static int vega20_print_clock_levels(struct pp_hwmgr *hwmgr, + return ret); + + size += sprintf(buf + size, "MCLK: %7uMhz %10uMhz\n", +- clocks.data[0].clocks_in_khz / 100, ++ clocks.data[0].clocks_in_khz / 1000, + od8_settings[OD8_SETTING_UCLK_FMAX].max_value); + } + +-- +2.17.1 + |