diff options
Diffstat (limited to 'common/recipes-kernel/linux/linux-yocto-4.19.8/0549-drm-amd-display-add-dccg-block.patch')
| -rw-r--r-- | common/recipes-kernel/linux/linux-yocto-4.19.8/0549-drm-amd-display-add-dccg-block.patch | 142 |
1 files changed, 142 insertions, 0 deletions
diff --git a/common/recipes-kernel/linux/linux-yocto-4.19.8/0549-drm-amd-display-add-dccg-block.patch b/common/recipes-kernel/linux/linux-yocto-4.19.8/0549-drm-amd-display-add-dccg-block.patch new file mode 100644 index 00000000..4e6a524a --- /dev/null +++ b/common/recipes-kernel/linux/linux-yocto-4.19.8/0549-drm-amd-display-add-dccg-block.patch @@ -0,0 +1,142 @@ +From 35d650a3504fc4b0057802a118156c7559af499d Mon Sep 17 00:00:00 2001 +From: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> +Date: Fri, 28 Sep 2018 08:42:52 -0400 +Subject: [PATCH 0549/2940] drm/amd/display: add dccg block + +This adds the hw block as well as hooks up dppclk dto +programming + +Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> +Reviewed-by: Charlene Liu <Charlene.Liu@amd.com> +Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> +--- + .../gpu/drm/amd/display/dc/dce/dce_clk_mgr.h | 7 ++- + .../amd/display/dc/dcn10/dcn10_hw_sequencer.c | 9 +++- + .../gpu/drm/amd/display/dc/inc/core_types.h | 1 + + drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h | 44 +++++++++++++++++++ + 4 files changed, 58 insertions(+), 3 deletions(-) + create mode 100644 drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h + +diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.h b/drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.h +index 2668d5645daa..046077797416 100644 +--- a/drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.h ++++ b/drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.h +@@ -27,7 +27,8 @@ + #ifndef _DCE_CLK_MGR_H_ + #define _DCE_CLK_MGR_H_ + +-#include "../inc/hw/clk_mgr.h" ++#include "clk_mgr.h" ++#include "dccg.h" + + #define MEMORY_TYPE_MULTIPLIER_CZ 4 + +@@ -79,6 +80,8 @@ struct dce_clk_mgr { + const struct clk_mgr_shift *clk_mgr_shift; + const struct clk_mgr_mask *clk_mgr_mask; + ++ struct dccg *dccg; ++ + struct state_dependent_clocks max_clks_by_state[DM_PP_CLOCKS_MAX_STATES]; + + int dentist_vco_freq_khz; +@@ -160,6 +163,6 @@ struct clk_mgr *dce112_clk_mgr_create( + + struct clk_mgr *dce120_clk_mgr_create(struct dc_context *ctx); + +-void dce_clk_mgr_destroy(struct clk_mgr **dccg); ++void dce_clk_mgr_destroy(struct clk_mgr **clk_mgr); + + #endif /* _DCE_CLK_MGR_H_ */ +diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c +index 5c4a4f68b8a0..f88c440c2826 100644 +--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c ++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c +@@ -45,6 +45,7 @@ + #include "dcn10_hubbub.h" + #include "dcn10_cm_common.h" + #include "dc_link_dp.h" ++#include "dccg.h" + + #define DC_LOGGER_INIT(logger) + +@@ -2059,7 +2060,13 @@ void update_dchubp_dpp( + should_divided_by_2, + true); + +- dc->res_pool->clk_mgr->clks.dppclk_khz = should_divided_by_2 ? ++ if (dc->res_pool->dccg) ++ dc->res_pool->dccg->funcs->update_dpp_dto( ++ dc->res_pool->dccg, ++ dpp->inst, ++ pipe_ctx->plane_res.bw.calc.dppclk_khz); ++ else ++ dc->res_pool->clk_mgr->clks.dppclk_khz = should_divided_by_2 ? + dc->res_pool->clk_mgr->clks.dispclk_khz / 2 : + dc->res_pool->clk_mgr->clks.dispclk_khz; + } +diff --git a/drivers/gpu/drm/amd/display/dc/inc/core_types.h b/drivers/gpu/drm/amd/display/dc/inc/core_types.h +index ca6818f8eb60..1baa0b1af5e3 100644 +--- a/drivers/gpu/drm/amd/display/dc/inc/core_types.h ++++ b/drivers/gpu/drm/amd/display/dc/inc/core_types.h +@@ -170,6 +170,7 @@ struct resource_pool { + struct audio_support audio_support; + + struct clk_mgr *clk_mgr; ++ struct dccg *dccg; + struct irq_service *irqs; + + struct abm *abm; +diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h b/drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h +new file mode 100644 +index 000000000000..95a56d012626 +--- /dev/null ++++ b/drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h +@@ -0,0 +1,44 @@ ++/* ++ * Copyright 2018 Advanced Micro Devices, Inc. ++ * ++ * Permission is hereby granted, free of charge, to any person obtaining a ++ * copy of this software and associated documentation files (the "Software"), ++ * to deal in the Software without restriction, including without limitation ++ * the rights to use, copy, modify, merge, publish, distribute, sublicense, ++ * and/or sell copies of the Software, and to permit persons to whom the ++ * Software is furnished to do so, subject to the following conditions: ++ * ++ * The above copyright notice and this permission notice shall be included in ++ * all copies or substantial portions of the Software. ++ * ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR ++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, ++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL ++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR ++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR ++ * OTHER DEALINGS IN THE SOFTWARE. ++ * ++ * Authors: AMD ++ * ++ */ ++ ++#ifndef __DAL_DCCG_H__ ++#define __DAL_DCCG_H__ ++ ++#include "dc_types.h" ++ ++struct dccg { ++ struct dc_context *ctx; ++ const struct dccg_funcs *funcs; ++ ++ int ref_dppclk; ++}; ++ ++struct dccg_funcs { ++ void (*update_dpp_dto)(struct dccg *dccg, ++ int dpp_inst, ++ int req_dppclk); ++}; ++ ++#endif //__DAL_DCCG_H__ +-- +2.17.1 + |