diff options
Diffstat (limited to 'common/recipes-kernel/linux/linux-yocto-4.19.8/0521-drm-amdgpu-vcn-Update-SPG-mode-VCN-global-tiling.patch')
-rw-r--r-- | common/recipes-kernel/linux/linux-yocto-4.19.8/0521-drm-amdgpu-vcn-Update-SPG-mode-VCN-global-tiling.patch | 46 |
1 files changed, 46 insertions, 0 deletions
diff --git a/common/recipes-kernel/linux/linux-yocto-4.19.8/0521-drm-amdgpu-vcn-Update-SPG-mode-VCN-global-tiling.patch b/common/recipes-kernel/linux/linux-yocto-4.19.8/0521-drm-amdgpu-vcn-Update-SPG-mode-VCN-global-tiling.patch new file mode 100644 index 00000000..218670ee --- /dev/null +++ b/common/recipes-kernel/linux/linux-yocto-4.19.8/0521-drm-amdgpu-vcn-Update-SPG-mode-VCN-global-tiling.patch @@ -0,0 +1,46 @@ +From c9e661914732171251c5829a93e044df09ce1f1a Mon Sep 17 00:00:00 2001 +From: James Zhu <James.Zhu@amd.com> +Date: Tue, 9 Oct 2018 16:43:32 -0400 +Subject: [PATCH 0521/2940] drm/amdgpu/vcn:Update SPG mode VCN global tiling + +Update Static Power Gate mode VCN global tiling + +Signed-off-by: James Zhu <James.Zhu@amd.com> +Acked-by: Leo Liu <leo.liu@amd.com> +Acked-by: Alex Deucher <alexander.deucher@amd.com> +--- + drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c | 18 ++++++++++++++++++ + 1 file changed, 18 insertions(+) + +diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c +index 73301a9dc37d..29f711b57506 100644 +--- a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c ++++ b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c +@@ -325,6 +325,24 @@ static void vcn_v1_0_mc_resume_spg_mode(struct amdgpu_device *adev) + adev->gfx.config.gb_addr_config); + WREG32_SOC15(UVD, 0, mmUVD_UDEC_DBW_ADDR_CONFIG, + adev->gfx.config.gb_addr_config); ++ WREG32_SOC15(UVD, 0, mmUVD_UDEC_DBW_UV_ADDR_CONFIG, ++ adev->gfx.config.gb_addr_config); ++ WREG32_SOC15(UVD, 0, mmUVD_MIF_CURR_ADDR_CONFIG, ++ adev->gfx.config.gb_addr_config); ++ WREG32_SOC15(UVD, 0, mmUVD_MIF_CURR_UV_ADDR_CONFIG, ++ adev->gfx.config.gb_addr_config); ++ WREG32_SOC15(UVD, 0, mmUVD_MIF_RECON1_ADDR_CONFIG, ++ adev->gfx.config.gb_addr_config); ++ WREG32_SOC15(UVD, 0, mmUVD_MIF_RECON1_UV_ADDR_CONFIG, ++ adev->gfx.config.gb_addr_config); ++ WREG32_SOC15(UVD, 0, mmUVD_MIF_REF_ADDR_CONFIG, ++ adev->gfx.config.gb_addr_config); ++ WREG32_SOC15(UVD, 0, mmUVD_MIF_REF_UV_ADDR_CONFIG, ++ adev->gfx.config.gb_addr_config); ++ WREG32_SOC15(UVD, 0, mmUVD_JPEG_ADDR_CONFIG, ++ adev->gfx.config.gb_addr_config); ++ WREG32_SOC15(UVD, 0, mmUVD_JPEG_UV_ADDR_CONFIG, ++ adev->gfx.config.gb_addr_config); + } + + static void vcn_v1_0_mc_resume_dpg_mode(struct amdgpu_device *adev) +-- +2.17.1 + |