diff options
Diffstat (limited to 'common/recipes-kernel/linux/linux-yocto-4.19.8/0515-drm-amdgpu-vcn-Update-DPG-mode-VCN-memory-control.patch')
| -rw-r--r-- | common/recipes-kernel/linux/linux-yocto-4.19.8/0515-drm-amdgpu-vcn-Update-DPG-mode-VCN-memory-control.patch | 58 |
1 files changed, 58 insertions, 0 deletions
diff --git a/common/recipes-kernel/linux/linux-yocto-4.19.8/0515-drm-amdgpu-vcn-Update-DPG-mode-VCN-memory-control.patch b/common/recipes-kernel/linux/linux-yocto-4.19.8/0515-drm-amdgpu-vcn-Update-DPG-mode-VCN-memory-control.patch new file mode 100644 index 00000000..edfc44ec --- /dev/null +++ b/common/recipes-kernel/linux/linux-yocto-4.19.8/0515-drm-amdgpu-vcn-Update-DPG-mode-VCN-memory-control.patch @@ -0,0 +1,58 @@ +From b48d7a24174daa24e2d42df8ea6c31a224c3b25a Mon Sep 17 00:00:00 2001 +From: James Zhu <James.Zhu@amd.com> +Date: Thu, 4 Oct 2018 15:10:52 -0400 +Subject: [PATCH 0515/2940] drm/amdgpu/vcn:Update DPG mode VCN memory control + +Update Dynamic Power Gate mode VCN memory control + +Signed-off-by: James Zhu <James.Zhu@amd.com> +Acked-by: Leo Liu <leo.liu@amd.com> +Acked-by: Alex Deucher <alexander.deucher@amd.com> +--- + drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c | 19 +++++++++++-------- + 1 file changed, 11 insertions(+), 8 deletions(-) + +diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c +index e597116d8282..0f3597c221c7 100644 +--- a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c ++++ b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c +@@ -983,11 +983,13 @@ static int vcn_v1_0_start_dpg_mode(struct amdgpu_device *adev) + + /* initialize VCN memory controller */ + WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_LMI_CTRL, +- (0x40 << UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT) | ++ (8 << UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT) | + UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK | + UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK | + UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK | + UVD_LMI_CTRL__REQ_MODE_MASK | ++ UVD_LMI_CTRL__CRC_RESET_MASK | ++ UVD_LMI_CTRL__MASK_MC_URGENT_MASK | + 0x00100000L, 0xFFFFFFFF, 0); + + #ifdef __BIG_ENDIAN +@@ -1041,13 +1043,14 @@ static int vcn_v1_0_start_dpg_mode(struct amdgpu_device *adev) + vcn_v1_0_clock_gating_dpg_mode(adev, 1); + /* setup mmUVD_LMI_CTRL */ + WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_LMI_CTRL, +- (UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK | +- UVD_LMI_CTRL__CRC_RESET_MASK | +- UVD_LMI_CTRL__MASK_MC_URGENT_MASK | +- UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK | +- UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK | +- (8 << UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT) | +- 0x00100000L), 0xFFFFFFFF, 1); ++ (8 << UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT) | ++ UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK | ++ UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK | ++ UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK | ++ UVD_LMI_CTRL__REQ_MODE_MASK | ++ UVD_LMI_CTRL__CRC_RESET_MASK | ++ UVD_LMI_CTRL__MASK_MC_URGENT_MASK | ++ 0x00100000L, 0xFFFFFFFF, 1); + + tmp = adev->gfx.config.gb_addr_config; + /* setup VCN global tiling registers */ +-- +2.17.1 + |