diff options
Diffstat (limited to 'common/recipes-kernel/linux/linux-yocto-4.19.8/0429-drm-amd-powerplay-tell-the-correct-gfx-voltage-V2.patch')
| -rw-r--r-- | common/recipes-kernel/linux/linux-yocto-4.19.8/0429-drm-amd-powerplay-tell-the-correct-gfx-voltage-V2.patch | 82 |
1 files changed, 82 insertions, 0 deletions
diff --git a/common/recipes-kernel/linux/linux-yocto-4.19.8/0429-drm-amd-powerplay-tell-the-correct-gfx-voltage-V2.patch b/common/recipes-kernel/linux/linux-yocto-4.19.8/0429-drm-amd-powerplay-tell-the-correct-gfx-voltage-V2.patch new file mode 100644 index 00000000..4bff6a02 --- /dev/null +++ b/common/recipes-kernel/linux/linux-yocto-4.19.8/0429-drm-amd-powerplay-tell-the-correct-gfx-voltage-V2.patch @@ -0,0 +1,82 @@ +From a24d14356784dd8a5743515d393a62c94feb1c82 Mon Sep 17 00:00:00 2001 +From: Evan Quan <evan.quan@amd.com> +Date: Mon, 17 Sep 2018 18:41:28 +0800 +Subject: [PATCH 0429/2940] drm/amd/powerplay: tell the correct gfx voltage V2 + +Export the correct gfx voltage by hwmon interface. + +V2: update the register naming for consistency + +Change-Id: I0390cadb2dc3423ffa4f09625e8abba8c4b5e230 +Signed-off-by: Evan Quan <evan.quan@amd.com> +Reviewed-by: Rex Zhu <Rex.Zhu@amd.com> +--- + .../amd/include/asic_reg/smuio/smuio_9_0_offset.h | 3 +++ + .../amd/include/asic_reg/smuio/smuio_9_0_sh_mask.h | 3 +++ + drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c | 12 ++++++++++++ + 3 files changed, 18 insertions(+) + +diff --git a/drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_9_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_9_0_offset.h +index efd2704d0f8f..0d6891095f62 100644 +--- a/drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_9_0_offset.h ++++ b/drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_9_0_offset.h +@@ -175,4 +175,7 @@ + #define mmSMUSVI0_PLANE0_CURRENTVID_BASE_IDX 0 + #define mmSMUSVI0_PLANE0_CURRENTVID 0x0013 + ++#define mmSMUSVI0_TEL_PLANE0_BASE_IDX 0 ++#define mmSMUSVI0_TEL_PLANE0 0x0004 ++ + #endif +diff --git a/drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_9_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_9_0_sh_mask.h +index 2487ab9621e9..b1d9d8be1119 100644 +--- a/drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_9_0_sh_mask.h ++++ b/drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_9_0_sh_mask.h +@@ -258,4 +258,7 @@ + #define SMUSVI0_PLANE0_CURRENTVID__CURRENT_SVI0_PLANE0_VID__SHIFT 0x18 + #define SMUSVI0_PLANE0_CURRENTVID__CURRENT_SVI0_PLANE0_VID_MASK 0xFF000000L + ++#define SMUSVI0_TEL_PLANE0__SVI0_PLANE0_VDDCOR__SHIFT 0x10 ++#define SMUSVI0_TEL_PLANE0__SVI0_PLANE0_VDDCOR_MASK 0x01FF0000L ++ + #endif +diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c +index 292631357427..6ece7d724a5b 100644 +--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c ++++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c +@@ -46,6 +46,9 @@ + #include "ppinterrupt.h" + #include "pp_overdriver.h" + #include "pp_thermal.h" ++#include "soc15_common.h" ++#include "smuio/smuio_9_0_offset.h" ++#include "smuio/smuio_9_0_sh_mask.h" + + static void vega20_set_default_registry_data(struct pp_hwmgr *hwmgr) + { +@@ -1915,6 +1918,8 @@ static int vega20_read_sensor(struct pp_hwmgr *hwmgr, int idx, + void *value, int *size) + { + struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend); ++ struct amdgpu_device *adev = hwmgr->adev; ++ uint32_t val_vid; + int ret = 0; + + switch (idx) { +@@ -1949,6 +1954,13 @@ static int vega20_read_sensor(struct pp_hwmgr *hwmgr, int idx, + *size = 16; + ret = vega20_get_gpu_power(hwmgr, (uint32_t *)value); + break; ++ case AMDGPU_PP_SENSOR_VDDGFX: ++ val_vid = (RREG32_SOC15(SMUIO, 0, mmSMUSVI0_TEL_PLANE0) & ++ SMUSVI0_TEL_PLANE0__SVI0_PLANE0_VDDCOR_MASK) >> ++ SMUSVI0_TEL_PLANE0__SVI0_PLANE0_VDDCOR__SHIFT; ++ *((uint32_t *)value) = ++ (uint32_t)convert_to_vddc((uint8_t)val_vid); ++ break; + case AMDGPU_PP_SENSOR_ENABLED_SMC_FEATURES_MASK: + ret = vega20_get_enabled_smc_features(hwmgr, (uint64_t *)value); + if (!ret) +-- +2.17.1 + |