diff options
Diffstat (limited to 'common/recipes-kernel/linux/linux-yocto-4.19.8/0420-drm-amdgpu-Add-DPG-mode-read-write-macro.patch')
| -rw-r--r-- | common/recipes-kernel/linux/linux-yocto-4.19.8/0420-drm-amdgpu-Add-DPG-mode-read-write-macro.patch | 53 |
1 files changed, 53 insertions, 0 deletions
diff --git a/common/recipes-kernel/linux/linux-yocto-4.19.8/0420-drm-amdgpu-Add-DPG-mode-read-write-macro.patch b/common/recipes-kernel/linux/linux-yocto-4.19.8/0420-drm-amdgpu-Add-DPG-mode-read-write-macro.patch new file mode 100644 index 00000000..7150991f --- /dev/null +++ b/common/recipes-kernel/linux/linux-yocto-4.19.8/0420-drm-amdgpu-Add-DPG-mode-read-write-macro.patch @@ -0,0 +1,53 @@ +From a07ce404cf0fb327ccd00f700c4f37703a3173fd Mon Sep 17 00:00:00 2001 +From: James Zhu <James.Zhu@amd.com> +Date: Mon, 10 Sep 2018 16:00:36 -0400 +Subject: [PATCH 0420/2940] drm/amdgpu:Add DPG mode read/write macro +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Some registers read/write needs program through SDRAM pool under +DPG mode. + +Signed-off-by: James Zhu <James.Zhu@amd.com> +Reviewed-by: Alex Deucher <alexander.deucher@amd.com> +Reviewed-by: Huang Rui <ray.huang@amd.com> +Acked-by: Christian König <christian.koenig@amd.com> +--- + drivers/gpu/drm/amd/amdgpu/soc15_common.h | 20 ++++++++++++++++++++ + 1 file changed, 20 insertions(+) + +diff --git a/drivers/gpu/drm/amd/amdgpu/soc15_common.h b/drivers/gpu/drm/amd/amdgpu/soc15_common.h +index f5d602540673..d35fac5b5a8a 100644 +--- a/drivers/gpu/drm/amd/amdgpu/soc15_common.h ++++ b/drivers/gpu/drm/amd/amdgpu/soc15_common.h +@@ -64,6 +64,26 @@ + } \ + } while (0) + ++#define RREG32_SOC15_DPG_MODE(ip, inst, reg, mask, sram_sel) \ ++ ({ WREG32_SOC15(ip, inst, mmUVD_DPG_LMA_MASK, mask); \ ++ WREG32_SOC15(ip, inst, mmUVD_DPG_LMA_CTL, \ ++ UVD_DPG_LMA_CTL__MASK_EN_MASK | \ ++ ((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg) \ ++ << UVD_DPG_LMA_CTL__READ_WRITE_ADDR__SHIFT) | \ ++ (sram_sel << UVD_DPG_LMA_CTL__SRAM_SEL__SHIFT)); \ ++ RREG32_SOC15(ip, inst, mmUVD_DPG_LMA_DATA); }) ++ ++#define WREG32_SOC15_DPG_MODE(ip, inst, reg, value, mask, sram_sel) \ ++ do { \ ++ WREG32_SOC15(ip, inst, mmUVD_DPG_LMA_DATA, value); \ ++ WREG32_SOC15(ip, inst, mmUVD_DPG_LMA_MASK, mask); \ ++ WREG32_SOC15(ip, inst, mmUVD_DPG_LMA_CTL, \ ++ UVD_DPG_LMA_CTL__READ_WRITE_MASK | \ ++ ((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg) \ ++ << UVD_DPG_LMA_CTL__READ_WRITE_ADDR__SHIFT) | \ ++ (sram_sel << UVD_DPG_LMA_CTL__SRAM_SEL__SHIFT)); \ ++ } while (0) ++ + #endif + + +-- +2.17.1 + |