diff options
Diffstat (limited to 'common/recipes-kernel/linux/linux-yocto-4.19.8/0406-drm-amd-pp-Disable-dpm-features-on-smu7-8-when-suspe.patch')
| -rw-r--r-- | common/recipes-kernel/linux/linux-yocto-4.19.8/0406-drm-amd-pp-Disable-dpm-features-on-smu7-8-when-suspe.patch | 121 |
1 files changed, 121 insertions, 0 deletions
diff --git a/common/recipes-kernel/linux/linux-yocto-4.19.8/0406-drm-amd-pp-Disable-dpm-features-on-smu7-8-when-suspe.patch b/common/recipes-kernel/linux/linux-yocto-4.19.8/0406-drm-amd-pp-Disable-dpm-features-on-smu7-8-when-suspe.patch new file mode 100644 index 00000000..cf44f27c --- /dev/null +++ b/common/recipes-kernel/linux/linux-yocto-4.19.8/0406-drm-amd-pp-Disable-dpm-features-on-smu7-8-when-suspe.patch @@ -0,0 +1,121 @@ +From 15369b20ea7d039248fbed4e8ede12bfb41302dc Mon Sep 17 00:00:00 2001 +From: Rex Zhu <Rex.Zhu@amd.com> +Date: Thu, 20 Sep 2018 16:47:06 +0800 +Subject: [PATCH 0406/2940] drm/amd/pp: Disable dpm features on smu7/8 when + suspend + +Need to disable dpm features before halt rlc. + +Acked-by: Alex Deucher <alexander.deucher@amd.com> +Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> +--- + .../gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c | 13 +++++++ + .../gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c | 37 ++++++++++--------- + 2 files changed, 32 insertions(+), 18 deletions(-) + +diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c +index 04b7da0e39a6..0bfb3b4025ca 100644 +--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c ++++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c +@@ -5035,6 +5035,18 @@ static int smu7_get_performance_level(struct pp_hwmgr *hwmgr, const struct pp_hw + return 0; + } + ++static int smu7_power_off_asic(struct pp_hwmgr *hwmgr) ++{ ++ int result; ++ ++ result = smu7_disable_dpm_tasks(hwmgr); ++ PP_ASSERT_WITH_CODE((0 == result), ++ "[disable_dpm_tasks] Failed to disable DPM!", ++ ); ++ ++ return result; ++} ++ + static const struct pp_hwmgr_func smu7_hwmgr_funcs = { + .backend_init = &smu7_hwmgr_backend_init, + .backend_fini = &smu7_hwmgr_backend_fini, +@@ -5092,6 +5104,7 @@ static const struct pp_hwmgr_func smu7_hwmgr_funcs = { + .get_power_profile_mode = smu7_get_power_profile_mode, + .set_power_profile_mode = smu7_set_power_profile_mode, + .get_performance_level = smu7_get_performance_level, ++ .power_off_asic = smu7_power_off_asic, + }; + + uint8_t smu7_get_sleep_divider_id_from_clock(uint32_t clock, +diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c +index 86b6a43e1c6a..fef111ddb736 100644 +--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c ++++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c +@@ -880,7 +880,7 @@ static int smu8_set_power_state_tasks(struct pp_hwmgr *hwmgr, const void *input) + smu8_update_low_mem_pstate(hwmgr, input); + + return 0; +-}; ++} + + + static int smu8_setup_asic_task(struct pp_hwmgr *hwmgr) +@@ -934,14 +934,6 @@ static void smu8_reset_cc6_data(struct pp_hwmgr *hwmgr) + hw_data->cc6_settings.cpu_pstate_disable = false; + } + +-static int smu8_power_off_asic(struct pp_hwmgr *hwmgr) +-{ +- smu8_power_up_display_clock_sys_pll(hwmgr); +- smu8_clear_nb_dpm_flag(hwmgr); +- smu8_reset_cc6_data(hwmgr); +- return 0; +-}; +- + static void smu8_program_voting_clients(struct pp_hwmgr *hwmgr) + { + cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, +@@ -1011,6 +1003,17 @@ static void smu8_reset_acp_boot_level(struct pp_hwmgr *hwmgr) + data->acp_boot_level = 0xff; + } + ++static int smu8_enable_dpm_tasks(struct pp_hwmgr *hwmgr) ++{ ++ smu8_program_voting_clients(hwmgr); ++ if (smu8_start_dpm(hwmgr)) ++ return -EINVAL; ++ smu8_program_bootup_state(hwmgr); ++ smu8_reset_acp_boot_level(hwmgr); ++ ++ return 0; ++} ++ + static int smu8_disable_dpm_tasks(struct pp_hwmgr *hwmgr) + { + smu8_disable_nb_dpm(hwmgr); +@@ -1020,18 +1023,16 @@ static int smu8_disable_dpm_tasks(struct pp_hwmgr *hwmgr) + return -EINVAL; + + return 0; +-}; ++} + +-static int smu8_enable_dpm_tasks(struct pp_hwmgr *hwmgr) ++static int smu8_power_off_asic(struct pp_hwmgr *hwmgr) + { +- smu8_program_voting_clients(hwmgr); +- if (smu8_start_dpm(hwmgr)) +- return -EINVAL; +- smu8_program_bootup_state(hwmgr); +- smu8_reset_acp_boot_level(hwmgr); +- ++ smu8_disable_dpm_tasks(hwmgr); ++ smu8_power_up_display_clock_sys_pll(hwmgr); ++ smu8_clear_nb_dpm_flag(hwmgr); ++ smu8_reset_cc6_data(hwmgr); + return 0; +-}; ++} + + static int smu8_apply_state_adjust_rules(struct pp_hwmgr *hwmgr, + struct pp_power_state *prequest_ps, +-- +2.17.1 + |