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Diffstat (limited to 'common/recipes-kernel/linux/linux-yocto-4.19.8/0252-drm-amdgpu-enable-mmhub-power-gating.patch')
-rw-r--r--common/recipes-kernel/linux/linux-yocto-4.19.8/0252-drm-amdgpu-enable-mmhub-power-gating.patch303
1 files changed, 303 insertions, 0 deletions
diff --git a/common/recipes-kernel/linux/linux-yocto-4.19.8/0252-drm-amdgpu-enable-mmhub-power-gating.patch b/common/recipes-kernel/linux/linux-yocto-4.19.8/0252-drm-amdgpu-enable-mmhub-power-gating.patch
new file mode 100644
index 00000000..6ec37fe5
--- /dev/null
+++ b/common/recipes-kernel/linux/linux-yocto-4.19.8/0252-drm-amdgpu-enable-mmhub-power-gating.patch
@@ -0,0 +1,303 @@
+From 45a4c6b305fcc33eaff28a1ad3405c1ec19ec8cc Mon Sep 17 00:00:00 2001
+From: Kenneth Feng <kenneth.feng@amd.com>
+Date: Mon, 20 Aug 2018 15:39:32 +0800
+Subject: [PATCH 0252/2940] drm/amdgpu: enable mmhub power gating
+
+Remove some functions due to the design change.
+All the mmhub power gating sequence is moved to
+smu fw.Driver sends the message to enable mmhub
+powergating.We can also skip the fw version check
+since the old fw version is in a very early stage
+and we don't use that fw for release.
+
+Signed-off-by: Kenneth Feng <kenneth.feng@amd.com>
+Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 1 -
+ drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c | 220 ------------------------
+ drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.h | 1 -
+ drivers/gpu/drm/amd/amdgpu/soc15.c | 2 +-
+ 4 files changed, 1 insertion(+), 223 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+index 8d6c30b6f528..378f5526df01 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+@@ -1083,7 +1083,6 @@ static int gmc_v9_0_gart_enable(struct amdgpu_device *adev)
+ switch (adev->asic_type) {
+ case CHIP_RAVEN:
+ case CHIP_PICASSO:
+- mmhub_v1_0_initialize_power_gating(adev);
+ mmhub_v1_0_update_power_gating(adev, true);
+ break;
+ default:
+diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
+index 8875e10186d6..59b67fa49948 100644
+--- a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
+@@ -254,236 +254,16 @@ static void mmhub_v1_0_program_invalidation(struct amdgpu_device *adev)
+ }
+ }
+
+-struct pctl_data {
+- uint32_t index;
+- uint32_t data;
+-};
+-
+-static const struct pctl_data pctl0_data[] = {
+- {0x0, 0x7a640},
+- {0x9, 0x2a64a},
+- {0xd, 0x2a680},
+- {0x11, 0x6a684},
+- {0x19, 0xea68e},
+- {0x29, 0xa69e},
+- {0x2b, 0x0010a6c0},
+- {0x3d, 0x83a707},
+- {0xc2, 0x8a7a4},
+- {0xcc, 0x1a7b8},
+- {0xcf, 0xfa7cc},
+- {0xe0, 0x17a7dd},
+- {0xf9, 0xa7dc},
+- {0xfb, 0x12a7f5},
+- {0x10f, 0xa808},
+- {0x111, 0x12a810},
+- {0x125, 0x7a82c}
+-};
+-#define PCTL0_DATA_LEN (ARRAY_SIZE(pctl0_data))
+-
+-#define PCTL0_RENG_EXEC_END_PTR 0x12d
+-#define PCTL0_STCTRL_REG_SAVE_RANGE0_BASE 0xa640
+-#define PCTL0_STCTRL_REG_SAVE_RANGE0_LIMIT 0xa833
+-
+-static const struct pctl_data pctl1_data[] = {
+- {0x0, 0x39a000},
+- {0x3b, 0x44a040},
+- {0x81, 0x2a08d},
+- {0x85, 0x6ba094},
+- {0xf2, 0x18a100},
+- {0x10c, 0x4a132},
+- {0x112, 0xca141},
+- {0x120, 0x2fa158},
+- {0x151, 0x17a1d0},
+- {0x16a, 0x1a1e9},
+- {0x16d, 0x13a1ec},
+- {0x182, 0x7a201},
+- {0x18b, 0x3a20a},
+- {0x190, 0x7a580},
+- {0x199, 0xa590},
+- {0x19b, 0x4a594},
+- {0x1a1, 0x1a59c},
+- {0x1a4, 0x7a82c},
+- {0x1ad, 0xfa7cc},
+- {0x1be, 0x17a7dd},
+- {0x1d7, 0x12a810},
+- {0x1eb, 0x4000a7e1},
+- {0x1ec, 0x5000a7f5},
+- {0x1ed, 0x4000a7e2},
+- {0x1ee, 0x5000a7dc},
+- {0x1ef, 0x4000a7e3},
+- {0x1f0, 0x5000a7f6},
+- {0x1f1, 0x5000a7e4}
+-};
+-#define PCTL1_DATA_LEN (ARRAY_SIZE(pctl1_data))
+-
+-#define PCTL1_RENG_EXEC_END_PTR 0x1f1
+-#define PCTL1_STCTRL_REG_SAVE_RANGE0_BASE 0xa000
+-#define PCTL1_STCTRL_REG_SAVE_RANGE0_LIMIT 0xa20d
+-#define PCTL1_STCTRL_REG_SAVE_RANGE1_BASE 0xa580
+-#define PCTL1_STCTRL_REG_SAVE_RANGE1_LIMIT 0xa59d
+-#define PCTL1_STCTRL_REG_SAVE_RANGE2_BASE 0xa82c
+-#define PCTL1_STCTRL_REG_SAVE_RANGE2_LIMIT 0xa833
+-
+-static void mmhub_v1_0_power_gating_write_save_ranges(struct amdgpu_device *adev)
+-{
+- uint32_t tmp = 0;
+-
+- /* PCTL0_STCTRL_REGISTER_SAVE_RANGE0 */
+- tmp = REG_SET_FIELD(tmp, PCTL0_STCTRL_REGISTER_SAVE_RANGE0,
+- STCTRL_REGISTER_SAVE_BASE,
+- PCTL0_STCTRL_REG_SAVE_RANGE0_BASE);
+- tmp = REG_SET_FIELD(tmp, PCTL0_STCTRL_REGISTER_SAVE_RANGE0,
+- STCTRL_REGISTER_SAVE_LIMIT,
+- PCTL0_STCTRL_REG_SAVE_RANGE0_LIMIT);
+- WREG32_SOC15(MMHUB, 0, mmPCTL0_STCTRL_REGISTER_SAVE_RANGE0, tmp);
+-
+- /* PCTL1_STCTRL_REGISTER_SAVE_RANGE0 */
+- tmp = 0;
+- tmp = REG_SET_FIELD(tmp, PCTL1_STCTRL_REGISTER_SAVE_RANGE0,
+- STCTRL_REGISTER_SAVE_BASE,
+- PCTL1_STCTRL_REG_SAVE_RANGE0_BASE);
+- tmp = REG_SET_FIELD(tmp, PCTL1_STCTRL_REGISTER_SAVE_RANGE0,
+- STCTRL_REGISTER_SAVE_LIMIT,
+- PCTL1_STCTRL_REG_SAVE_RANGE0_LIMIT);
+- WREG32_SOC15(MMHUB, 0, mmPCTL1_STCTRL_REGISTER_SAVE_RANGE0, tmp);
+-
+- /* PCTL1_STCTRL_REGISTER_SAVE_RANGE1 */
+- tmp = 0;
+- tmp = REG_SET_FIELD(tmp, PCTL1_STCTRL_REGISTER_SAVE_RANGE1,
+- STCTRL_REGISTER_SAVE_BASE,
+- PCTL1_STCTRL_REG_SAVE_RANGE1_BASE);
+- tmp = REG_SET_FIELD(tmp, PCTL1_STCTRL_REGISTER_SAVE_RANGE1,
+- STCTRL_REGISTER_SAVE_LIMIT,
+- PCTL1_STCTRL_REG_SAVE_RANGE1_LIMIT);
+- WREG32_SOC15(MMHUB, 0, mmPCTL1_STCTRL_REGISTER_SAVE_RANGE1, tmp);
+-
+- /* PCTL1_STCTRL_REGISTER_SAVE_RANGE2 */
+- tmp = 0;
+- tmp = REG_SET_FIELD(tmp, PCTL1_STCTRL_REGISTER_SAVE_RANGE2,
+- STCTRL_REGISTER_SAVE_BASE,
+- PCTL1_STCTRL_REG_SAVE_RANGE2_BASE);
+- tmp = REG_SET_FIELD(tmp, PCTL1_STCTRL_REGISTER_SAVE_RANGE2,
+- STCTRL_REGISTER_SAVE_LIMIT,
+- PCTL1_STCTRL_REG_SAVE_RANGE2_LIMIT);
+- WREG32_SOC15(MMHUB, 0, mmPCTL1_STCTRL_REGISTER_SAVE_RANGE2, tmp);
+-}
+-
+-void mmhub_v1_0_initialize_power_gating(struct amdgpu_device *adev)
+-{
+- uint32_t pctl0_misc = 0;
+- uint32_t pctl0_reng_execute = 0;
+- uint32_t pctl1_misc = 0;
+- uint32_t pctl1_reng_execute = 0;
+- int i = 0;
+-
+- if (amdgpu_sriov_vf(adev))
+- return;
+-
+- /****************** pctl0 **********************/
+- pctl0_misc = RREG32_SOC15(MMHUB, 0, mmPCTL0_MISC);
+- pctl0_reng_execute = RREG32_SOC15(MMHUB, 0, mmPCTL0_RENG_EXECUTE);
+-
+- /* Light sleep must be disabled before writing to pctl0 registers */
+- pctl0_misc &= ~PCTL0_MISC__RENG_MEM_LS_ENABLE_MASK;
+- WREG32_SOC15(MMHUB, 0, mmPCTL0_MISC, pctl0_misc);
+-
+- /* Write data used to access ram of register engine */
+- for (i = 0; i < PCTL0_DATA_LEN; i++) {
+- WREG32_SOC15(MMHUB, 0, mmPCTL0_RENG_RAM_INDEX,
+- pctl0_data[i].index);
+- WREG32_SOC15(MMHUB, 0, mmPCTL0_RENG_RAM_DATA,
+- pctl0_data[i].data);
+- }
+-
+- /* Re-enable light sleep */
+- pctl0_misc |= PCTL0_MISC__RENG_MEM_LS_ENABLE_MASK;
+- WREG32_SOC15(MMHUB, 0, mmPCTL0_MISC, pctl0_misc);
+-
+- /****************** pctl1 **********************/
+- pctl1_misc = RREG32_SOC15(MMHUB, 0, mmPCTL1_MISC);
+- pctl1_reng_execute = RREG32_SOC15(MMHUB, 0, mmPCTL1_RENG_EXECUTE);
+-
+- /* Light sleep must be disabled before writing to pctl1 registers */
+- pctl1_misc &= ~PCTL1_MISC__RENG_MEM_LS_ENABLE_MASK;
+- WREG32_SOC15(MMHUB, 0, mmPCTL1_MISC, pctl1_misc);
+-
+- /* Write data used to access ram of register engine */
+- for (i = 0; i < PCTL1_DATA_LEN; i++) {
+- WREG32_SOC15(MMHUB, 0, mmPCTL1_RENG_RAM_INDEX,
+- pctl1_data[i].index);
+- WREG32_SOC15(MMHUB, 0, mmPCTL1_RENG_RAM_DATA,
+- pctl1_data[i].data);
+- }
+-
+- /* Re-enable light sleep */
+- pctl1_misc |= PCTL1_MISC__RENG_MEM_LS_ENABLE_MASK;
+- WREG32_SOC15(MMHUB, 0, mmPCTL1_MISC, pctl1_misc);
+-
+- mmhub_v1_0_power_gating_write_save_ranges(adev);
+-
+- /* Set the reng execute end ptr for pctl0 */
+- pctl0_reng_execute = REG_SET_FIELD(pctl0_reng_execute,
+- PCTL0_RENG_EXECUTE,
+- RENG_EXECUTE_END_PTR,
+- PCTL0_RENG_EXEC_END_PTR);
+- WREG32_SOC15(MMHUB, 0, mmPCTL0_RENG_EXECUTE, pctl0_reng_execute);
+-
+- /* Set the reng execute end ptr for pctl1 */
+- pctl1_reng_execute = REG_SET_FIELD(pctl1_reng_execute,
+- PCTL1_RENG_EXECUTE,
+- RENG_EXECUTE_END_PTR,
+- PCTL1_RENG_EXEC_END_PTR);
+- WREG32_SOC15(MMHUB, 0, mmPCTL1_RENG_EXECUTE, pctl1_reng_execute);
+-}
+-
+ void mmhub_v1_0_update_power_gating(struct amdgpu_device *adev,
+ bool enable)
+ {
+- uint32_t pctl0_reng_execute = 0;
+- uint32_t pctl1_reng_execute = 0;
+-
+ if (amdgpu_sriov_vf(adev))
+ return;
+
+- pctl0_reng_execute = RREG32_SOC15(MMHUB, 0, mmPCTL0_RENG_EXECUTE);
+- pctl1_reng_execute = RREG32_SOC15(MMHUB, 0, mmPCTL1_RENG_EXECUTE);
+-
+ if (enable && adev->pg_flags & AMD_PG_SUPPORT_MMHUB) {
+- pctl0_reng_execute = REG_SET_FIELD(pctl0_reng_execute,
+- PCTL0_RENG_EXECUTE,
+- RENG_EXECUTE_ON_PWR_UP, 1);
+- pctl0_reng_execute = REG_SET_FIELD(pctl0_reng_execute,
+- PCTL0_RENG_EXECUTE,
+- RENG_EXECUTE_ON_REG_UPDATE, 1);
+- WREG32_SOC15(MMHUB, 0, mmPCTL0_RENG_EXECUTE, pctl0_reng_execute);
+-
+- pctl1_reng_execute = REG_SET_FIELD(pctl1_reng_execute,
+- PCTL1_RENG_EXECUTE,
+- RENG_EXECUTE_ON_PWR_UP, 1);
+- pctl1_reng_execute = REG_SET_FIELD(pctl1_reng_execute,
+- PCTL1_RENG_EXECUTE,
+- RENG_EXECUTE_ON_REG_UPDATE, 1);
+- WREG32_SOC15(MMHUB, 0, mmPCTL1_RENG_EXECUTE, pctl1_reng_execute);
+-
+ if (adev->powerplay.pp_funcs->set_powergating_by_smu)
+ amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_GMC, true);
+
+- } else {
+- pctl0_reng_execute = REG_SET_FIELD(pctl0_reng_execute,
+- PCTL0_RENG_EXECUTE,
+- RENG_EXECUTE_ON_PWR_UP, 0);
+- pctl0_reng_execute = REG_SET_FIELD(pctl0_reng_execute,
+- PCTL0_RENG_EXECUTE,
+- RENG_EXECUTE_ON_REG_UPDATE, 0);
+- WREG32_SOC15(MMHUB, 0, mmPCTL0_RENG_EXECUTE, pctl0_reng_execute);
+-
+- pctl1_reng_execute = REG_SET_FIELD(pctl1_reng_execute,
+- PCTL1_RENG_EXECUTE,
+- RENG_EXECUTE_ON_PWR_UP, 0);
+- pctl1_reng_execute = REG_SET_FIELD(pctl1_reng_execute,
+- PCTL1_RENG_EXECUTE,
+- RENG_EXECUTE_ON_REG_UPDATE, 0);
+- WREG32_SOC15(MMHUB, 0, mmPCTL1_RENG_EXECUTE, pctl1_reng_execute);
+ }
+ }
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.h b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.h
+index 5d38229baf69..bef3d0c0c117 100644
+--- a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.h
++++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.h
+@@ -32,7 +32,6 @@ void mmhub_v1_0_init(struct amdgpu_device *adev);
+ int mmhub_v1_0_set_clockgating(struct amdgpu_device *adev,
+ enum amd_clockgating_state state);
+ void mmhub_v1_0_get_clockgating(struct amdgpu_device *adev, u32 *flags);
+-void mmhub_v1_0_initialize_power_gating(struct amdgpu_device *adev);
+ void mmhub_v1_0_update_power_gating(struct amdgpu_device *adev,
+ bool enable);
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c
+index e00b76d80c07..a646c77f3165 100644
+--- a/drivers/gpu/drm/amd/amdgpu/soc15.c
++++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
+@@ -740,7 +740,7 @@ static int soc15_common_early_init(void *handle)
+ AMD_CG_SUPPORT_SDMA_MGCG |
+ AMD_CG_SUPPORT_SDMA_LS;
+
+- adev->pg_flags = AMD_PG_SUPPORT_SDMA;
++ adev->pg_flags = AMD_PG_SUPPORT_SDMA | AMD_PG_SUPPORT_MMHUB;
+
+ if (adev->powerplay.pp_feature & PP_GFXOFF_MASK)
+ adev->pg_flags |= AMD_PG_SUPPORT_GFX_PG |
+--
+2.17.1
+